Skip to content
A tiny Open POWER ISA softcore written in VHDL 2008
VHDL C Makefile Other
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
fpga ram: Rework main RAM interface Oct 30, 2019
hello_world Rebuild hello world assuming a 50MHz clock Aug 26, 2019
media Add title image Oct 9, 2019
scripts
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs Sep 20, 2019
tests
.gitignore
.travis.yml Allow a full make check on Travis Sep 11, 2019
LICENSE
Makefile
README.md ram: Rework main RAM interface Oct 30, 2019
cache_ram.vhdl dcache: Introduce an extra cycle latency to make timing Oct 23, 2019
common.vhdl
control.vhdl control: Reduce pipeline depth to 1 Nov 14, 2019
core.vhdl Add option to not flatten hierarchy Oct 30, 2019
core_debug.vhdl
core_tb.vhdl ram: Rework main RAM interface Oct 30, 2019
countzero.vhdl countzero: Reorganize to have fewer levels of logic and fewer LUTs Oct 13, 2019
countzero_tb.vhdl countzero: Add a testbench Oct 13, 2019
cr_file.vhdl Reformat CR file Sep 19, 2019
cr_hazard.vhdl Add CR hazard detection Oct 15, 2019
crhelpers.vhdl crhelpers: Constraint "crnum" integer Oct 16, 2019
dcache.vhdl
dcache_tb.vhdl ram: Rework main RAM interface Oct 30, 2019
decode1.vhdl insn: Simplistic implementation of icbi Oct 23, 2019
decode2.vhdl control: Reduce pipeline depth to 1 Nov 14, 2019
decode_types.vhdl decode: Reformat decode_types.vhdl Oct 30, 2019
divider.vhdl
divider_tb.vhdl writeback: Do data formatting and condition recording in writeback Oct 15, 2019
dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl ram: Rework main RAM interface Oct 30, 2019
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously Sep 30, 2019
execute1.vhdl spr: Cleanup decoding of SPR numbers Nov 14, 2019
fetch1.vhdl fetch/icache: Fit icache in BRAM Oct 8, 2019
fetch2.vhdl fetch2: Remove blank line Oct 8, 2019
glibc_random.vhdl Reformat glibc_random Sep 19, 2019
glibc_random_helpers.vhdl
gpr_hazard.vhdl Add GPR hazard detection Oct 14, 2019
helpers.vhdl
icache.vhdl Move log2/ispow2 to a utils package Oct 30, 2019
icache_tb.vhdl ram: Rework main RAM interface Oct 30, 2019
icache_test.bin icache_tb: Improve test and include test file Oct 18, 2019
insn_helpers.vhdl Add MCRF instruction Oct 1, 2019
loadstore1.vhdl
logical.vhdl
microwatt.core ram: Rework main RAM interface Oct 30, 2019
multiply.vhdl writeback: Do data formatting and condition recording in writeback Oct 15, 2019
multiply_tb.vhdl writeback: Do data formatting and condition recording in writeback Oct 15, 2019
plru.vhdl
plru_tb.vhdl plru: Add a simple PLRU module Oct 8, 2019
ppc_fx_insns.vhdl
register_file.vhdl Fix register file size (there are 32 gprs). Oct 12, 2019
rotator.vhdl
rotator_tb.vhdl
sim_bram.vhdl ram: Rework main RAM interface Oct 30, 2019
sim_bram_helpers.vhdl ram: Rework main RAM interface Oct 30, 2019
sim_bram_helpers_c.c ram: Rework main RAM interface Oct 30, 2019
sim_console.vhdl
sim_console_c.c Make sim poll non-blocking Sep 9, 2019
sim_jtag.vhdl Add jtag support in simulation via a socket Sep 20, 2019
sim_jtag_socket.vhdl Add jtag support in simulation via a socket Sep 20, 2019
sim_jtag_socket_c.c debug/sim: Make connect/disconnect messages quieter Oct 1, 2019
sim_uart.vhdl Share soc.vhdl between FPGA and sim Sep 10, 2019
soc.vhdl
utils.vhdl
wishbone_arbiter.vhdl wb_arbiter: Early master selection Oct 31, 2019
wishbone_bram_tb.bin ram: Rework main RAM interface Oct 30, 2019
wishbone_bram_tb.vhdl ram: Rework main RAM interface Oct 30, 2019
wishbone_bram_wrapper.vhdl ram: Ack stores early Oct 30, 2019
wishbone_debug_master.vhdl
wishbone_types.vhdl
writeback.vhdl writeback: Slightly improve timing Oct 30, 2019

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)
You can’t perform that action at this time.