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ram: Rework main RAM interface

This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
  • Loading branch information
ozbenh committed Oct 23, 2019
1 parent 9a63c09 commit 8e0389b9736c60572e13ef5eeb50d3a775c3ffc6
@@ -2,8 +2,8 @@ GHDL=ghdl
GHDLFLAGS=--std=08 -Psim-unisim
CFLAGS=-O2 -Wall

all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
rotator_tb countzero_tb
all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
rotator_tb countzero_tb wishbone_bram_tb

# XXX
# loadstore_tb fetch_tb
@@ -35,11 +35,14 @@ helpers.o:
cache_ram.o:
plru.o:
plru_tb.o: plru.o
icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o
dcache_tb.o: common.o wishbone_types.o dcache.o simple_ram_behavioural.o
utils.o:
sim_bram.o: sim_bram_helpers.o utils.o
wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
wishbone_bram_tb.o: wishbone_bram_wrapper.o
icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
insn_helpers.o:
loadstore1.o: common.o helpers.o
logical.o: decode_types.o
@@ -52,11 +55,8 @@ register_file.o: common.o
rotator.o: common.o
rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
sim_console.o:
simple_ram_behavioural_helpers.o:
simple_ram_behavioural_tb.o: wishbone_types.o simple_ram_behavioural.o
simple_ram_behavioural.o: wishbone_types.o simple_ram_behavioural_helpers.o
sim_uart.o: wishbone_types.o sim_console.o
soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o simple_ram_behavioural.o dmi_dtm_xilinx.o wishbone_debug_master.o
soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o
wishbone_arbiter.o: wishbone_types.o
wishbone_types.o:
writeback.o: common.o crhelpers.o
@@ -74,17 +74,17 @@ fpga/soc_reset_tb.o: fpga/soc_reset.o
soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
$(GHDL) -e $(GHDLFLAGS) soc_reset_tb

core_tb: core_tb.o simple_ram_behavioural_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
core_tb: core_tb.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@

fetch_tb: fetch_tb.o
$(GHDL) -e $(GHDLFLAGS) $@

icache_tb: icache_tb.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@

dcache_tb: dcache_tb.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@

plru_tb: plru_tb.o
$(GHDL) -e $(GHDLFLAGS) $@
@@ -107,11 +107,11 @@ countzero_tb: countzero_tb.o
simple_ram_tb: simple_ram_tb.o
$(GHDL) -e $(GHDLFLAGS) $@

simple_ram_behavioural_tb: simple_ram_behavioural_helpers_c.o simple_ram_behavioural_tb.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
wishbone_bram_tb: sim_bram_helpers_c.o wishbone_bram_tb.o
$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@

dmi_dtm_tb: dmi_dtm_tb.o simple_ram_behavioural_helpers_c.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
dmi_dtm_tb: dmi_dtm_tb.o sim_bram_helpers_c.o
$(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@

tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))

@@ -39,7 +39,7 @@ make
- Link in the micropython image:

```
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
```

- Now run microwatt, sending debug output to /dev/null:
@@ -20,7 +20,7 @@ begin
generic map(
SIM => true,
MEMORY_SIZE => 524288,
RAM_INIT_FILE => "simple_ram_behavioural.bin",
RAM_INIT_FILE => "main_ram.bin",
RESET_LOW => false
)
port map(
@@ -35,9 +35,9 @@ begin
);

-- BRAM Memory slave
bram0: entity work.mw_soc_memory
bram0: entity work.wishbone_bram_wrapper
generic map(
MEMORY_SIZE => 128,
MEMORY_SIZE => 1024,
RAM_INIT_FILE => "icache_test.bin"
)
port map(
@@ -121,7 +121,6 @@ begin
d_in.valid <= '1';
wait until rising_edge(clk);
d_in.valid <= '0';

wait until rising_edge(clk) and d_out.write_enable = '1';
assert d_out.valid = '1';
assert d_out.write_data = x"0000004100000040"
@@ -130,7 +129,10 @@ begin
" expected 0000004100000040"
severity failure;

wait for clk_period*4;
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);

assert false report "end of test" severity failure;
wait;
@@ -50,8 +50,8 @@ begin
dmi_ack => dmi_ack
);

simple_ram_0: entity work.mw_soc_memory
generic map(RAM_INIT_FILE => "simple_ram_behavioural.bin",
simple_ram_0: entity work.wishbone_bram_wrapper
generic map(RAM_INIT_FILE => "main_ram.bin",
MEMORY_SIZE => 524288)
port map(clk => clk, rst => rst,
wishbone_in => wishbone_ram_out,
@@ -0,0 +1,83 @@
-- Single port Block RAM with one cycle output buffer

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;

library work;

entity main_bram is
generic(
WIDTH : natural := 64;
HEIGHT_BITS : natural := 1024;
MEMORY_SIZE : natural := 65536;
RAM_INIT_FILE : string
);
port(
clk : in std_logic;
addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
di : in std_logic_vector(WIDTH-1 downto 0);
do : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic_vector((WIDTH/8)-1 downto 0);
re : in std_ulogic;
we : in std_ulogic
);
end entity main_bram;

architecture behaviour of main_bram is

constant WIDTH_BYTES : natural := WIDTH / 8;

-- RAM type definition
type ram_t is array(0 to (MEMORY_SIZE / WIDTH_BYTES) - 1) of std_logic_vector(WIDTH-1 downto 0);

-- RAM loading
impure function init_ram(name : STRING) return ram_t is
file ram_file : text open read_mode is name;
variable ram_line : line;
variable temp_word : std_logic_vector(WIDTH-1 downto 0);
variable temp_ram : ram_t := (others => (others => '0'));
begin
for i in 0 to (MEMORY_SIZE / WIDTH_BYTES) - 1 loop
exit when endfile(ram_file);
readline(ram_file, ram_line);
hread(ram_line, temp_word);
temp_ram(i) := temp_word;
end loop;

return temp_ram;
end function;

-- RAM instance
signal memory : ram_t := init_ram(RAM_INIT_FILE);
attribute ram_style : string;
attribute ram_style of memory : signal is "block";
attribute ram_decomp : string;
attribute ram_decomp of memory : signal is "power";

-- Others
signal obuf : std_logic_vector(WIDTH-1 downto 0);
begin

-- Actual RAM template
memory_0: process(clk)
begin
if rising_edge(clk) then
if we = '1' then
for i in 0 to 7 loop
if sel(i) = '1' then
memory(conv_integer(addr))((i + 1) * 8 - 1 downto i * 8) <=
di((i + 1) * 8 - 1 downto i * 8);
end if;
end loop;
end if;
if re = '1' then
obuf <= memory(conv_integer(addr));
end if;
do <= obuf;
end if;
end process;

end architecture behaviour;

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