xtensa: some fixes in interrupt handler #5248
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Hi @zhuyanlinzyl did you test BUILD_PROTECTED ? |
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hi, @acassis. |
xiaoxiang781216
approved these changes
Jan 18, 2022
1. error in A3 push stack 2. when interrupt stack enable, push a12 is xtensa_irq_dispatch parameter 1, instead of sp. As sp is interrupt stack address set by `setintstack`, not the interruptee stack address Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
svcall.c for xtensa Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
As in _xtensa_syscall_handler, a3 was save and reused before _xtensa_context_save, a3 save in _xtensa_context_save will generate error. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
When enable interrupt stack, use a12 instead of sp Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
Use right EXCSAVE_X Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
| call0 _xtensa_context_save /* Save full register state */ | ||
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| /* Dispatch the sycall as with other interrupts. */ |
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Suggested change
| /* Dispatch the sycall as with other interrupts. */ | |
| /* Dispatch the syscall as with other interrupts. */ |
Ouss4
approved these changes
Jan 19, 2022
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Summary
Five patches include:
xtensa: fix svccall enter error
xtensa: add svcall handler
xtensa: move a3 save in handler instead of _xtensa_context_save
arch:xtensa_panic: use right interrupt pointer in xtensa_panic
arch:xtensa:vectors:fix bugs in a0 save
Impac
No, bug fix.
Testing
Testing on xtensa EVB borad