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arm/armv7-a: Remove CONFIG_SMP guard from arm_scu.c #5620

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merged 1 commit into from Feb 26, 2022

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xiaoxiang781216
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@xiaoxiang781216 xiaoxiang781216 commented Feb 25, 2022

Summary

since ACTLR.SMP need enable to make cache work on Cortex A7:
https://developer.arm.com/documentation/ddi0464/f/CHDBIEIF

Impact

Minor

Testing

Pass CI

since ACTLR.SMP need enable to make cache work on Cortex A7:
https://developer.arm.com/documentation/ddi0464/f/CHDBIEIF

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
@masayuki2009
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masayuki2009 commented Feb 26, 2022

@xiaoxiang781216

How about the Cortex-A8 case which has no SCU?
I think that the SCU exists only on the MPCore.

@xiaoxiang781216
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@xiaoxiang781216

How about the Cortex-A8 case which has no SCU? I think that the SCU exists only on the MPCore.

Yes, but sometime, it's useful to run independent NuttX instance on each PMCore. If SCU function is guarded by CONFIG_SMP, we lose this possibility. On the other hand, arm_scu.c just contain passive utility functions, the chip developer should have enough knowledge to know whether to call these functions.

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@xiaoxiang781216

I noticed that arm_enable_smp() is currently called in arch/arm/src/imx6 only.
So, for example, am335x which has Cortex-A8 would not be affected.

@masayuki2009 masayuki2009 merged commit b95022f into apache:master Feb 26, 2022
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@xiaoxiang781216

I noticed that arm_enable_smp() is currently called in arch/arm/src/imx6 only. So, for example, am335x which has Cortex-A8 would not be affected.

Yes, where to call arm_enable_smp is controlled by the chip code, not arch common code.

@jerpelea jerpelea added this to To-Add in Release Notes - 10.3.0 Mar 15, 2022
@jerpelea jerpelea moved this from To-Add to Minor in Release Notes - 10.3.0 Mar 17, 2022
@jerpelea jerpelea moved this from Minor to In Progress in Release Notes - 10.3.0 Mar 22, 2022
@jerpelea jerpelea moved this from In Progress to added in Release Notes - 10.3.0 Mar 22, 2022
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2 participants