This repository was archived by the owner on May 22, 2023. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 1.7k
Expand file tree
/
Copy pathpmap.c
More file actions
10555 lines (8913 loc) · 270 KB
/
pmap.c
File metadata and controls
10555 lines (8913 loc) · 270 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2011-2016 Apple Inc. All rights reserved.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
* compliance with the License. The rights granted to you under the License
* may not be used to create, or enable the creation or redistribution of,
* unlawful or unlicensed copies of an Apple operating system, or to
* circumvent, violate, or enable the circumvention or violation of, any
* terms of an Apple operating system software license agreement.
*
* Please obtain a copy of the License at
* http://www.opensource.apple.com/apsl/ and read it before using this file.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
* Please see the License for the specific language governing rights and
* limitations under the License.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
#include <string.h>
#include <mach_assert.h>
#include <mach_ldebug.h>
#include <mach/shared_region.h>
#include <mach/vm_param.h>
#include <mach/vm_prot.h>
#include <mach/vm_map.h>
#include <mach/machine/vm_param.h>
#include <mach/machine/vm_types.h>
#include <mach/boolean.h>
#include <kern/thread.h>
#include <kern/sched.h>
#include <kern/zalloc.h>
#include <kern/kalloc.h>
#include <kern/ledger.h>
#include <kern/misc_protos.h>
#include <kern/spl.h>
#include <kern/xpr.h>
#include <vm/pmap.h>
#include <vm/vm_map.h>
#include <vm/vm_kern.h>
#include <vm/vm_protos.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>
#include <vm/cpm.h>
#include <libkern/section_keywords.h>
#include <machine/atomic.h>
#include <machine/thread.h>
#include <machine/lowglobals.h>
#include <arm/caches_internal.h>
#include <arm/cpu_data.h>
#include <arm/cpu_data_internal.h>
#include <arm/cpu_capabilities.h>
#include <arm/cpu_number.h>
#include <arm/machine_cpu.h>
#include <arm/misc_protos.h>
#include <arm/trap.h>
#include <libkern/section_keywords.h>
#if (__ARM_VMSA__ > 7)
#include <arm64/proc_reg.h>
#include <pexpert/arm64/boot.h>
#if CONFIG_PGTRACE
#include <stdint.h>
#include <arm64/pgtrace.h>
#if CONFIG_PGTRACE_NONKEXT
#include <arm64/pgtrace_decoder.h>
#endif // CONFIG_PGTRACE_NONKEXT
#endif
#endif
#include <pexpert/device_tree.h>
#include <san/kasan.h>
#if DEVELOPMENT || DEBUG
#define PMAP_FOOTPRINT_SUSPENDED(pmap) ((pmap)->footprint_suspended)
#else /* DEVELOPMENT || DEBUG */
#define PMAP_FOOTPRINT_SUSPENDED(pmap) (FALSE)
#endif /* DEVELOPMENT || DEBUG */
#if DEVELOPMENT || DEBUG
int panic_on_unsigned_execute = 0;
#endif /* DEVELOPMENT || DEBUG */
/* Virtual memory region for early allocation */
#if (__ARM_VMSA__ == 7)
#define VREGION1_START (VM_HIGH_KERNEL_WINDOW & ~ARM_TT_L1_PT_OFFMASK)
#else
#define VREGION1_HIGH_WINDOW (PE_EARLY_BOOT_VA)
#define VREGION1_START ((VM_MAX_KERNEL_ADDRESS & CPUWINDOWS_BASE_MASK) - VREGION1_HIGH_WINDOW)
#endif
#define VREGION1_SIZE (trunc_page(VM_MAX_KERNEL_ADDRESS - (VREGION1_START)))
extern unsigned int not_in_kdp;
extern vm_offset_t first_avail;
extern pmap_paddr_t avail_start;
extern pmap_paddr_t avail_end;
extern vm_offset_t virtual_space_start; /* Next available kernel VA */
extern vm_offset_t virtual_space_end; /* End of kernel address space */
extern int hard_maxproc;
#if (__ARM_VMSA__ > 7)
/* The number of address bits one TTBR can cover. */
#define PGTABLE_ADDR_BITS (64ULL - T0SZ_BOOT)
/*
* The bounds on our TTBRs. These are for sanity checking that
* an address is accessible by a TTBR before we attempt to map it.
*/
#define ARM64_TTBR0_MIN_ADDR (0ULL)
#define ARM64_TTBR0_MAX_ADDR (0ULL + (1ULL << PGTABLE_ADDR_BITS) - 1)
#define ARM64_TTBR1_MIN_ADDR (0ULL - (1ULL << PGTABLE_ADDR_BITS))
#define ARM64_TTBR1_MAX_ADDR (~0ULL)
/* The level of the root of a page table. */
const uint64_t arm64_root_pgtable_level = (3 - ((PGTABLE_ADDR_BITS - 1 - ARM_PGSHIFT) / (ARM_PGSHIFT - TTE_SHIFT)));
/* The number of entries in the root TT of a page table. */
const uint64_t arm64_root_pgtable_num_ttes = (2 << ((PGTABLE_ADDR_BITS - 1 - ARM_PGSHIFT) % (ARM_PGSHIFT - TTE_SHIFT)));
#else
const uint64_t arm64_root_pgtable_level = 0;
const uint64_t arm64_root_pgtable_num_ttes = 0;
#endif
struct pmap kernel_pmap_store MARK_AS_PMAP_DATA;
SECURITY_READ_ONLY_LATE(pmap_t) kernel_pmap = &kernel_pmap_store;
struct vm_object pmap_object_store __attribute__((aligned(VM_PACKED_POINTER_ALIGNMENT))); /* store pt pages */
vm_object_t pmap_object = &pmap_object_store;
static struct zone *pmap_zone; /* zone of pmap structures */
decl_simple_lock_data(, pmaps_lock MARK_AS_PMAP_DATA)
unsigned int pmap_stamp MARK_AS_PMAP_DATA;
queue_head_t map_pmap_list MARK_AS_PMAP_DATA;
queue_head_t tt_pmap_list MARK_AS_PMAP_DATA;
unsigned int tt_pmap_count MARK_AS_PMAP_DATA;
unsigned int tt_pmap_max MARK_AS_PMAP_DATA;
decl_simple_lock_data(, pt_pages_lock MARK_AS_PMAP_DATA)
queue_head_t pt_page_list MARK_AS_PMAP_DATA; /* pt page ptd entries list */
decl_simple_lock_data(, pmap_pages_lock MARK_AS_PMAP_DATA)
typedef struct page_free_entry {
struct page_free_entry *next;
} page_free_entry_t;
#define PAGE_FREE_ENTRY_NULL ((page_free_entry_t *) 0)
page_free_entry_t *pmap_pages_reclaim_list MARK_AS_PMAP_DATA; /* Reclaimed pt page list */
unsigned int pmap_pages_request_count MARK_AS_PMAP_DATA; /* Pending requests to reclaim pt page */
unsigned long long pmap_pages_request_acum MARK_AS_PMAP_DATA;
typedef struct tt_free_entry {
struct tt_free_entry *next;
} tt_free_entry_t;
#define TT_FREE_ENTRY_NULL ((tt_free_entry_t *) 0)
tt_free_entry_t *free_page_size_tt_list MARK_AS_PMAP_DATA;
unsigned int free_page_size_tt_count MARK_AS_PMAP_DATA;
unsigned int free_page_size_tt_max MARK_AS_PMAP_DATA;
#define FREE_PAGE_SIZE_TT_MAX 4
tt_free_entry_t *free_two_page_size_tt_list MARK_AS_PMAP_DATA;
unsigned int free_two_page_size_tt_count MARK_AS_PMAP_DATA;
unsigned int free_two_page_size_tt_max MARK_AS_PMAP_DATA;
#define FREE_TWO_PAGE_SIZE_TT_MAX 4
tt_free_entry_t *free_tt_list MARK_AS_PMAP_DATA;
unsigned int free_tt_count MARK_AS_PMAP_DATA;
unsigned int free_tt_max MARK_AS_PMAP_DATA;
#define TT_FREE_ENTRY_NULL ((tt_free_entry_t *) 0)
boolean_t pmap_gc_allowed MARK_AS_PMAP_DATA = TRUE;
boolean_t pmap_gc_forced MARK_AS_PMAP_DATA = FALSE;
boolean_t pmap_gc_allowed_by_time_throttle = TRUE;
unsigned int inuse_user_ttepages_count MARK_AS_PMAP_DATA = 0; /* non-root, non-leaf user pagetable pages, in units of PAGE_SIZE */
unsigned int inuse_user_ptepages_count MARK_AS_PMAP_DATA = 0; /* leaf user pagetable pages, in units of PAGE_SIZE */
unsigned int inuse_user_tteroot_count MARK_AS_PMAP_DATA = 0; /* root user pagetables, in units of PMAP_ROOT_ALLOC_SIZE */
unsigned int inuse_kernel_ttepages_count MARK_AS_PMAP_DATA = 0; /* non-root, non-leaf kernel pagetable pages, in units of PAGE_SIZE */
unsigned int inuse_kernel_ptepages_count MARK_AS_PMAP_DATA = 0; /* leaf kernel pagetable pages, in units of PAGE_SIZE */
unsigned int inuse_kernel_tteroot_count MARK_AS_PMAP_DATA = 0; /* root kernel pagetables, in units of PMAP_ROOT_ALLOC_SIZE */
unsigned int inuse_pmap_pages_count = 0; /* debugging */
SECURITY_READ_ONLY_LATE(tt_entry_t *) invalid_tte = 0;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) invalid_ttep = 0;
SECURITY_READ_ONLY_LATE(tt_entry_t *) cpu_tte = 0; /* set by arm_vm_init() - keep out of bss */
SECURITY_READ_ONLY_LATE(pmap_paddr_t) cpu_ttep = 0; /* set by arm_vm_init() - phys tte addr */
#if DEVELOPMENT || DEBUG
int nx_enabled = 1; /* enable no-execute protection */
int allow_data_exec = 0; /* No apps may execute data */
int allow_stack_exec = 0; /* No apps may execute from the stack */
#else /* DEVELOPMENT || DEBUG */
const int nx_enabled = 1; /* enable no-execute protection */
const int allow_data_exec = 0; /* No apps may execute data */
const int allow_stack_exec = 0; /* No apps may execute from the stack */
#endif /* DEVELOPMENT || DEBUG */
/*
* pv_entry_t - structure to track the active mappings for a given page
*/
typedef struct pv_entry {
struct pv_entry *pve_next; /* next alias */
pt_entry_t *pve_ptep; /* page table entry */
#if __arm__ && (__BIGGEST_ALIGNMENT__ > 4)
/* For the newer ARMv7k ABI where 64-bit types are 64-bit aligned, but pointers
* are 32-bit:
* Since pt_desc is 64-bit aligned and we cast often from pv_entry to
* pt_desc.
*/
} __attribute__ ((aligned(8))) pv_entry_t;
#else
} pv_entry_t;
#endif
#define PV_ENTRY_NULL ((pv_entry_t *) 0)
/*
* PMAP LEDGERS:
* We use the least significant bit of the "pve_next" pointer in a "pv_entry"
* as a marker for pages mapped through an "alternate accounting" mapping.
* These macros set, clear and test for this marker and extract the actual
* value of the "pve_next" pointer.
*/
#define PVE_NEXT_ALTACCT ((uintptr_t) 0x1)
#define PVE_NEXT_SET_ALTACCT(pve_next_p) \
*(pve_next_p) = (struct pv_entry *) (((uintptr_t) *(pve_next_p)) | \
PVE_NEXT_ALTACCT)
#define PVE_NEXT_CLR_ALTACCT(pve_next_p) \
*(pve_next_p) = (struct pv_entry *) (((uintptr_t) *(pve_next_p)) & \
~PVE_NEXT_ALTACCT)
#define PVE_NEXT_IS_ALTACCT(pve_next) \
((((uintptr_t) (pve_next)) & PVE_NEXT_ALTACCT) ? TRUE : FALSE)
#define PVE_NEXT_PTR(pve_next) \
((struct pv_entry *)(((uintptr_t) (pve_next)) & \
~PVE_NEXT_ALTACCT))
#if MACH_ASSERT
static void pmap_check_ledgers(pmap_t pmap);
#else
static inline void pmap_check_ledgers(__unused pmap_t pmap) {}
#endif /* MACH_ASSERT */
SECURITY_READ_ONLY_LATE(pv_entry_t **) pv_head_table; /* array of pv entry pointers */
pv_entry_t *pv_free_list MARK_AS_PMAP_DATA;
pv_entry_t *pv_kern_free_list MARK_AS_PMAP_DATA;
decl_simple_lock_data(,pv_free_list_lock MARK_AS_PMAP_DATA)
decl_simple_lock_data(,pv_kern_free_list_lock MARK_AS_PMAP_DATA)
decl_simple_lock_data(,phys_backup_lock)
/*
* pt_desc - structure to keep info on page assigned to page tables
*/
#if (__ARM_VMSA__ == 7)
#define PT_INDEX_MAX 1
#else
#if (ARM_PGSHIFT == 14)
#define PT_INDEX_MAX 1
#else
#define PT_INDEX_MAX 4
#endif
#endif
#define PT_DESC_REFCOUNT 0x4000U
typedef struct pt_desc {
queue_chain_t pt_page;
struct {
unsigned short refcnt;
unsigned short wiredcnt;
} pt_cnt[PT_INDEX_MAX];
struct pmap *pmap;
struct {
vm_offset_t va;
} pt_map[PT_INDEX_MAX];
} pt_desc_t;
#define PTD_ENTRY_NULL ((pt_desc_t *) 0)
SECURITY_READ_ONLY_LATE(pt_desc_t *) ptd_root_table;
pt_desc_t *ptd_free_list MARK_AS_PMAP_DATA = PTD_ENTRY_NULL;
SECURITY_READ_ONLY_LATE(boolean_t) ptd_preboot = TRUE;
unsigned int ptd_free_count MARK_AS_PMAP_DATA = 0;
decl_simple_lock_data(,ptd_free_list_lock MARK_AS_PMAP_DATA)
/*
* physical page attribute
*/
typedef u_int16_t pp_attr_t;
#define PP_ATTR_WIMG_MASK 0x003F
#define PP_ATTR_WIMG(x) ((x) & PP_ATTR_WIMG_MASK)
#define PP_ATTR_REFERENCED 0x0040
#define PP_ATTR_MODIFIED 0x0080
#define PP_ATTR_INTERNAL 0x0100
#define PP_ATTR_REUSABLE 0x0200
#define PP_ATTR_ALTACCT 0x0400
#define PP_ATTR_NOENCRYPT 0x0800
#define PP_ATTR_REFFAULT 0x1000
#define PP_ATTR_MODFAULT 0x2000
SECURITY_READ_ONLY_LATE(pp_attr_t*) pp_attr_table;
typedef uint8_t io_attr_t;
#define IO_ATTR_WIMG_MASK 0x3F
#define IO_ATTR_WIMG(x) ((x) & IO_ATTR_WIMG_MASK)
SECURITY_READ_ONLY_LATE(io_attr_t*) io_attr_table;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) vm_first_phys = (pmap_paddr_t) 0;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) vm_last_phys = (pmap_paddr_t) 0;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) io_rgn_start = 0;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) io_rgn_end = 0;
SECURITY_READ_ONLY_LATE(uint32_t) io_rgn_granule = 0;
SECURITY_READ_ONLY_LATE(boolean_t) pmap_initialized = FALSE; /* Has pmap_init completed? */
SECURITY_READ_ONLY_LATE(uint64_t) pmap_nesting_size_min;
SECURITY_READ_ONLY_LATE(uint64_t) pmap_nesting_size_max;
SECURITY_READ_ONLY_LATE(vm_map_offset_t) arm_pmap_max_offset_default = 0x0;
#if defined(__arm64__)
SECURITY_READ_ONLY_LATE(vm_map_offset_t) arm64_pmap_max_offset_default = 0x0;
#endif
/* free address spaces (1 means free) */
static uint32_t asid_bitmap[MAX_ASID / (sizeof(uint32_t) * NBBY)] MARK_AS_PMAP_DATA;
#if (__ARM_VMSA__ > 7)
SECURITY_READ_ONLY_LATE(pmap_t) u32_sharedpage_pmap;
#endif
#define pa_index(pa) \
(atop((pa) - vm_first_phys))
#define pai_to_pvh(pai) \
(&pv_head_table[pai])
#define pa_valid(x) \
((x) >= vm_first_phys && (x) < vm_last_phys)
/* PTE Define Macros */
#define pte_is_wired(pte) \
(((pte) & ARM_PTE_WIRED_MASK) == ARM_PTE_WIRED)
#define pte_set_wired(ptep, wired) \
do { \
SInt16 *ptd_wiredcnt_ptr; \
ptd_wiredcnt_ptr = (SInt16 *)&(ptep_get_ptd(ptep)->pt_cnt[ARM_PT_DESC_INDEX(ptep)].wiredcnt); \
if (wired) { \
*ptep |= ARM_PTE_WIRED; \
OSAddAtomic16(1, ptd_wiredcnt_ptr); \
} else { \
*ptep &= ~ARM_PTE_WIRED; \
OSAddAtomic16(-1, ptd_wiredcnt_ptr); \
} \
} while(0)
#define pte_is_ffr(pte) \
(((pte) & ARM_PTE_WRITEABLE) == ARM_PTE_WRITEABLE)
#define pte_set_ffr(pte, ffr) \
do { \
if (ffr) { \
pte |= ARM_PTE_WRITEABLE; \
} else { \
pte &= ~ARM_PTE_WRITEABLE; \
} \
} while(0)
/* PVE Define Macros */
#define pve_next(pve) \
((pve)->pve_next)
#define pve_link_field(pve) \
(&pve_next(pve))
#define pve_link(pp, e) \
((pve_next(e) = pve_next(pp)), (pve_next(pp) = (e)))
#define pve_unlink(pp, e) \
(pve_next(pp) = pve_next(e))
/* bits held in the ptep pointer field */
#define pve_get_ptep(pve) \
((pve)->pve_ptep)
#define pve_set_ptep(pve, ptep_new) \
do { \
(pve)->pve_ptep = (ptep_new); \
} while (0)
/* PTEP Define Macros */
#if (__ARM_VMSA__ == 7)
#define ARM_PT_DESC_INDEX_MASK 0x00000
#define ARM_PT_DESC_INDEX_SHIFT 0
/*
* mask for page descriptor index: 4MB per page table
*/
#define ARM_TT_PT_INDEX_MASK 0xfffU /* mask for page descriptor index: 4MB per page table */
/*
* Shift value used for reconstructing the virtual address for a PTE.
*/
#define ARM_TT_PT_ADDR_SHIFT (10U)
#define ARM_PT_DESC_INDEX(ptep) \
(((unsigned)(ptep) & ARM_PT_DESC_INDEX_MASK) >> ARM_PT_DESC_INDEX_SHIFT)
#define ptep_get_ptd(ptep) \
((struct pt_desc *)((*((vm_offset_t *)(pai_to_pvh(pa_index((vm_offset_t)(ptep) - gVirtBase + gPhysBase))))) & PVH_LIST_MASK))
#define ptep_get_va(ptep) \
((((pt_desc_t *) (pvh_list(pai_to_pvh(pa_index((((vm_offset_t)(ptep) & ~0xFFF) - gVirtBase + gPhysBase))))))->pt_map[ARM_PT_DESC_INDEX(ptep)].va)+ ((((unsigned)(ptep)) & ARM_TT_PT_INDEX_MASK)<<ARM_TT_PT_ADDR_SHIFT))
#define ptep_get_pmap(ptep) \
((((pt_desc_t *) (pvh_list(pai_to_pvh(pa_index((((vm_offset_t)(ptep) & ~0xFFF) - gVirtBase + gPhysBase))))))->pmap))
#else
#if (ARM_PGSHIFT == 12)
#define ARM_PT_DESC_INDEX_MASK ((PAGE_SHIFT_CONST == ARM_PGSHIFT )? 0x00000ULL : 0x03000ULL)
#define ARM_PT_DESC_INDEX_SHIFT ((PAGE_SHIFT_CONST == ARM_PGSHIFT )? 0 : 12)
/*
* mask for page descriptor index: 2MB per page table
*/
#define ARM_TT_PT_INDEX_MASK (0x0fffULL)
/*
* Shift value used for reconstructing the virtual address for a PTE.
*/
#define ARM_TT_PT_ADDR_SHIFT (9ULL)
/* TODO: Give this a better name/documentation than "other" */
#define ARM_TT_PT_OTHER_MASK (0x0fffULL)
#else
#define ARM_PT_DESC_INDEX_MASK (0x00000)
#define ARM_PT_DESC_INDEX_SHIFT (0)
/*
* mask for page descriptor index: 32MB per page table
*/
#define ARM_TT_PT_INDEX_MASK (0x3fffULL)
/*
* Shift value used for reconstructing the virtual address for a PTE.
*/
#define ARM_TT_PT_ADDR_SHIFT (11ULL)
/* TODO: Give this a better name/documentation than "other" */
#define ARM_TT_PT_OTHER_MASK (0x3fffULL)
#endif
#define ARM_PT_DESC_INDEX(ptep) \
(((unsigned)(ptep) & ARM_PT_DESC_INDEX_MASK) >> ARM_PT_DESC_INDEX_SHIFT)
#define ptep_get_ptd(ptep) \
((struct pt_desc *)((*((vm_offset_t *)(pai_to_pvh(pa_index((vm_offset_t)(ptep) - gVirtBase + gPhysBase))))) & PVH_LIST_MASK))
#define ptep_get_va(ptep) \
((((pt_desc_t *) (pvh_list(pai_to_pvh(pa_index((((vm_offset_t)(ptep) & ~ARM_TT_PT_OTHER_MASK) - gVirtBase + gPhysBase))))))->pt_map[ARM_PT_DESC_INDEX(ptep)].va)+ ((((unsigned)(ptep)) & ARM_TT_PT_INDEX_MASK)<<ARM_TT_PT_ADDR_SHIFT))
#define ptep_get_pmap(ptep) \
((((pt_desc_t *) (pvh_list(pai_to_pvh(pa_index((((vm_offset_t)(ptep) & ~ARM_TT_PT_OTHER_MASK) - gVirtBase + gPhysBase))))))->pmap))
#endif
/* PVH Define Macros */
/* pvhead type */
#define PVH_TYPE_NULL 0x0UL
#define PVH_TYPE_PVEP 0x1UL
#define PVH_TYPE_PTEP 0x2UL
#define PVH_TYPE_PTDP 0x3UL
#define PVH_TYPE_MASK (0x3UL)
#define PVH_LIST_MASK (~PVH_TYPE_MASK)
#if (__ARM_VMSA__ == 7)
#define pvh_set_bits(h, b) \
do { \
while (!OSCompareAndSwap(*(vm_offset_t *)(h), *(vm_offset_t *)(h) | (b), (vm_offset_t *)(h))); \
} while (0)
#define pvh_clear_bits(h, b) \
do { \
while (!OSCompareAndSwap(*(vm_offset_t *)(h), *(vm_offset_t *)(h) & ~(b), (vm_offset_t *)(h))); \
} while (0)
#else
#define pvh_set_bits(h, b) \
do { \
while (!OSCompareAndSwap64(*(vm_offset_t *)(h), *(vm_offset_t *)(h) | ((int64_t)b), (vm_offset_t *)(h))); \
} while (0)
#define pvh_clear_bits(h, b) \
do { \
while (!OSCompareAndSwap64(*(vm_offset_t *)(h), *(vm_offset_t *)(h) & ~((int64_t)b), (vm_offset_t *)(h))); \
} while (0)
#endif
#define pvh_test_type(h, b) \
((*(vm_offset_t *)(h) & (PVH_TYPE_MASK)) == (b))
#define pvh_ptep(h) \
((pt_entry_t *)(*(vm_offset_t *)(h) & PVH_LIST_MASK))
#define pvh_list(h) \
((pv_entry_t *)(*(vm_offset_t *)(h) & PVH_LIST_MASK))
#define pvh_bits(h) \
(*(vm_offset_t *)(h) & PVH_TYPE_MASK)
#if (__ARM_VMSA__ == 7)
#define pvh_update_head(h, e, t) \
do { \
while (!OSCompareAndSwap(*(vm_offset_t *)(h), (vm_offset_t)(e) | (t), (vm_offset_t *)(h))); \
} while (0)
#else
#define pvh_update_head(h, e, t) \
do { \
while (!OSCompareAndSwap64(*(vm_offset_t *)(h), (vm_offset_t)(e) | (t), (vm_offset_t *)(h))); \
} while (0)
#endif
#define pvh_add(h, e) \
do { \
assert(!pvh_test_type((h), PVH_TYPE_PTEP)); \
pve_next(e) = pvh_list(h); \
pvh_update_head((h), (e), PVH_TYPE_PVEP); \
} while (0)
#define pvh_remove(h, p, e) \
do { \
assert(!PVE_NEXT_IS_ALTACCT(pve_next((e)))); \
if ((p) == (h)) { \
if (PVE_NEXT_PTR(pve_next((e))) == PV_ENTRY_NULL) { \
pvh_update_head((h), PV_ENTRY_NULL, PVH_TYPE_NULL); \
} else { \
pvh_update_head((h), PVE_NEXT_PTR(pve_next((e))), PVH_TYPE_PVEP); \
} \
} else { \
/* \
* PMAP LEDGERS: \
* preserve the "alternate accounting" bit \
* when updating "p" (the previous entry's \
* "pve_next"). \
*/ \
boolean_t __is_altacct; \
__is_altacct = PVE_NEXT_IS_ALTACCT(*(p)); \
*(p) = PVE_NEXT_PTR(pve_next((e))); \
if (__is_altacct) { \
PVE_NEXT_SET_ALTACCT((p)); \
} else { \
PVE_NEXT_CLR_ALTACCT((p)); \
} \
} \
} while (0)
/* PPATTR Define Macros */
#define ppattr_set_bits(h, b) \
do { \
while (!OSCompareAndSwap16(*(pp_attr_t *)(h), *(pp_attr_t *)(h) | (b), (pp_attr_t *)(h))); \
} while (0)
#define ppattr_clear_bits(h, b) \
do { \
while (!OSCompareAndSwap16(*(pp_attr_t *)(h), *(pp_attr_t *)(h) & ~(b), (pp_attr_t *)(h))); \
} while (0)
#define ppattr_test_bits(h, b) \
((*(pp_attr_t *)(h) & (b)) == (b))
#define pa_set_bits(x, b) \
do { \
if (pa_valid(x)) \
ppattr_set_bits(&pp_attr_table[pa_index(x)], \
(b)); \
} while (0)
#define pa_test_bits(x, b) \
(pa_valid(x) ? ppattr_test_bits(&pp_attr_table[pa_index(x)],\
(b)) : FALSE)
#define pa_clear_bits(x, b) \
do { \
if (pa_valid(x)) \
ppattr_clear_bits(&pp_attr_table[pa_index(x)], \
(b)); \
} while (0)
#define pa_set_modify(x) \
pa_set_bits(x, PP_ATTR_MODIFIED)
#define pa_clear_modify(x) \
pa_clear_bits(x, PP_ATTR_MODIFIED)
#define pa_set_reference(x) \
pa_set_bits(x, PP_ATTR_REFERENCED)
#define pa_clear_reference(x) \
pa_clear_bits(x, PP_ATTR_REFERENCED)
#define IS_INTERNAL_PAGE(pai) \
ppattr_test_bits(&pp_attr_table[pai], PP_ATTR_INTERNAL)
#define SET_INTERNAL_PAGE(pai) \
ppattr_set_bits(&pp_attr_table[pai], PP_ATTR_INTERNAL)
#define CLR_INTERNAL_PAGE(pai) \
ppattr_clear_bits(&pp_attr_table[pai], PP_ATTR_INTERNAL)
#define IS_REUSABLE_PAGE(pai) \
ppattr_test_bits(&pp_attr_table[pai], PP_ATTR_REUSABLE)
#define SET_REUSABLE_PAGE(pai) \
ppattr_set_bits(&pp_attr_table[pai], PP_ATTR_REUSABLE)
#define CLR_REUSABLE_PAGE(pai) \
ppattr_clear_bits(&pp_attr_table[pai], PP_ATTR_REUSABLE)
#define IS_ALTACCT_PAGE(pai, pve_p) \
(((pve_p) == NULL) \
? ppattr_test_bits(&pp_attr_table[pai], PP_ATTR_ALTACCT) \
: PVE_NEXT_IS_ALTACCT(pve_next((pve_p))))
#define SET_ALTACCT_PAGE(pai, pve_p) \
if ((pve_p) == NULL) { \
ppattr_set_bits(&pp_attr_table[pai], PP_ATTR_ALTACCT); \
} else { \
PVE_NEXT_SET_ALTACCT(&pve_next((pve_p))); \
}
#define CLR_ALTACCT_PAGE(pai, pve_p) \
if ((pve_p) == NULL) { \
ppattr_clear_bits(&pp_attr_table[pai], PP_ATTR_ALTACCT);\
} else { \
PVE_NEXT_CLR_ALTACCT(&pve_next((pve_p))); \
}
#define IS_REFFAULT_PAGE(pai) \
ppattr_test_bits(&pp_attr_table[pai], PP_ATTR_REFFAULT)
#define SET_REFFAULT_PAGE(pai) \
ppattr_set_bits(&pp_attr_table[pai], PP_ATTR_REFFAULT)
#define CLR_REFFAULT_PAGE(pai) \
ppattr_clear_bits(&pp_attr_table[pai], PP_ATTR_REFFAULT)
#define IS_MODFAULT_PAGE(pai) \
ppattr_test_bits(&pp_attr_table[pai], PP_ATTR_MODFAULT)
#define SET_MODFAULT_PAGE(pai) \
ppattr_set_bits(&pp_attr_table[pai], PP_ATTR_MODFAULT)
#define CLR_MODFAULT_PAGE(pai) \
ppattr_clear_bits(&pp_attr_table[pai], PP_ATTR_MODFAULT)
#if (__ARM_VMSA__ == 7)
#define tte_index(pmap, addr) \
ttenum((addr))
#define tte_get_ptd(tte) \
((struct pt_desc *)((*((vm_offset_t *)(pai_to_pvh(pa_index((vm_offset_t)((tte) & ~PAGE_MASK)))))) & PVH_LIST_MASK))
#else
#define tt0_index(pmap, addr) \
(((addr) & ARM_TT_L0_INDEX_MASK) >> ARM_TT_L0_SHIFT)
#define tt1_index(pmap, addr) \
(((addr) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT)
#define tt2_index(pmap, addr) \
(((addr) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)
#define tt3_index(pmap, addr) \
(((addr) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT)
#define tte_index(pmap, addr) \
(((addr) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)
#define tte_get_ptd(tte) \
((struct pt_desc *)((*((vm_offset_t *)(pai_to_pvh(pa_index((vm_offset_t)((tte) & ~PAGE_MASK)))))) & PVH_LIST_MASK))
#endif
/*
* Lock on pmap system
*/
#define PMAP_LOCK_INIT(pmap) { \
simple_lock_init(&(pmap)->lock, 0); \
}
#define PMAP_LOCK(pmap) { \
simple_lock(&(pmap)->lock); \
}
#define PMAP_UNLOCK(pmap) { \
simple_unlock(&(pmap)->lock); \
}
#if MACH_ASSERT
#define PMAP_ASSERT_LOCKED(pmap) { \
simple_lock_assert(&(pmap)->lock, LCK_ASSERT_OWNED); \
}
#else
#define PMAP_ASSERT_LOCKED(pmap)
#endif
/*
* Each entry in the pv_head_table is locked by a bit in the
* pv lock array, which is stored in the region preceding pv_head_table.
* The lock bits are accessed by the physical address of the page they lock.
*/
#define LOCK_PVH(index) { \
hw_lock_bit((hw_lock_bit_t *) \
((unsigned int*)pv_head_table)-1-(index>>5), \
(index&0x1F)); \
}
#define UNLOCK_PVH(index) { \
hw_unlock_bit((hw_lock_bit_t *) \
((unsigned int*)pv_head_table)-1-(index>>5), \
(index&0x1F)); \
}
#define ASSERT_PVH_LOCKED(index) { \
assert(*(((unsigned int*)pv_head_table)-1-(index>>5)) & (1 << (index & 0x1F))); \
}
#define PMAP_UPDATE_TLBS(pmap, s, e) { \
flush_mmu_tlb_region_asid(s, (unsigned)(e - s), pmap); \
}
#ifdef __ARM_L1_PTW__
#define FLUSH_PTE_RANGE(spte, epte) \
__asm__ volatile("dsb ish");
#define FLUSH_PTE(pte_p) \
__asm__ volatile("dsb ish");
#else
#define FLUSH_PTE_RANGE(spte, epte) \
CleanPoU_DcacheRegion((vm_offset_t)spte, \
(vm_offset_t)epte - (vm_offset_t)spte);
#define FLUSH_PTE(pte_p) \
CleanPoU_DcacheRegion((vm_offset_t)pte_p, sizeof(pt_entry_t));
#endif
#define WRITE_PTE(pte_p, pte_entry) \
__unreachable_ok_push \
if (TEST_PAGE_RATIO_4) { \
do { \
if (((unsigned)(pte_p)) & 0x1f) panic("WRITE_PTE\n"); \
if (((pte_entry) & ~ARM_PTE_COMPRESSED_MASK) == ARM_PTE_EMPTY) { \
*(pte_p) = (pte_entry); \
*((pte_p)+1) = (pte_entry); \
*((pte_p)+2) = (pte_entry); \
*((pte_p)+3) = (pte_entry); \
} else { \
*(pte_p) = (pte_entry); \
*((pte_p)+1) = (pte_entry) | 0x1000; \
*((pte_p)+2) = (pte_entry) | 0x2000; \
*((pte_p)+3) = (pte_entry) | 0x3000; \
} \
FLUSH_PTE_RANGE((pte_p),((pte_p)+4)); \
} while(0); \
} else { \
do { \
*(pte_p) = (pte_entry); \
FLUSH_PTE(pte_p); \
} while(0); \
} \
__unreachable_ok_pop
#define WRITE_PTE_FAST(pte_p, pte_entry) \
__unreachable_ok_push \
if (TEST_PAGE_RATIO_4) { \
if (((unsigned)(pte_p)) & 0x1f) panic("WRITE_PTE\n"); \
if (((pte_entry) & ~ARM_PTE_COMPRESSED_MASK) == ARM_PTE_EMPTY) { \
*(pte_p) = (pte_entry); \
*((pte_p)+1) = (pte_entry); \
*((pte_p)+2) = (pte_entry); \
*((pte_p)+3) = (pte_entry); \
} else { \
*(pte_p) = (pte_entry); \
*((pte_p)+1) = (pte_entry) | 0x1000; \
*((pte_p)+2) = (pte_entry) | 0x2000; \
*((pte_p)+3) = (pte_entry) | 0x3000; \
} \
} else { \
*(pte_p) = (pte_entry); \
} \
__unreachable_ok_pop
/*
* Other useful macros.
*/
#define current_pmap() \
(vm_map_pmap(current_thread()->map))
#define PMAP_IS_VALID(x) (TRUE)
#ifdef PMAP_TRACES
unsigned int pmap_trace = 0;
#define PMAP_TRACE(...) \
if (pmap_trace) { \
KDBG_RELEASE(__VA_ARGS__); \
}
#else
#define PMAP_TRACE(...) KDBG_DEBUG(__VA_ARGS__)
#endif
#define PMAP_TRACE_CONSTANT(...) KDBG_RELEASE(__VA_ARGS__)
/*
* Internal function prototypes (forward declarations).
*/
static void pv_init(
void);
static boolean_t pv_alloc(
pmap_t pmap,
unsigned int pai,
pv_entry_t **pvepp);
static void pv_free(
pv_entry_t *pvep);
static void pv_list_free(
pv_entry_t *pvehp,
pv_entry_t *pvetp,
unsigned int cnt);
static void ptd_bootstrap(
pt_desc_t *ptdp, unsigned int ptd_cnt);
static pt_desc_t *ptd_alloc(
pmap_t pmap);
static void ptd_deallocate(
pt_desc_t *ptdp);
static void ptd_init(
pt_desc_t *ptdp, pmap_t pmap, vm_map_address_t va, unsigned int ttlevel, pt_entry_t * pte_p);
static void pmap_zone_init(
void);
static void pmap_set_reference(
ppnum_t pn);
ppnum_t pmap_vtophys(
pmap_t pmap, addr64_t va);
void pmap_switch_user_ttb(
pmap_t pmap);
static void flush_mmu_tlb_region_asid(
vm_offset_t va, unsigned length, pmap_t pmap);
static kern_return_t pmap_expand(
pmap_t, vm_map_address_t, unsigned int options, unsigned int level);
static int pmap_remove_range(
pmap_t, vm_map_address_t, pt_entry_t *, pt_entry_t *, uint32_t *);
static int pmap_remove_range_options(
pmap_t, vm_map_address_t, pt_entry_t *, pt_entry_t *, uint32_t *, int);
static tt_entry_t *pmap_tt1_allocate(
pmap_t, vm_size_t, unsigned int);
#define PMAP_TT_ALLOCATE_NOWAIT 0x1
static void pmap_tt1_deallocate(
pmap_t, tt_entry_t *, vm_size_t, unsigned int);
#define PMAP_TT_DEALLOCATE_NOBLOCK 0x1
static kern_return_t pmap_tt_allocate(
pmap_t, tt_entry_t **, unsigned int, unsigned int);
#define PMAP_TT_ALLOCATE_NOWAIT 0x1
static void pmap_tte_deallocate(
pmap_t, tt_entry_t *, unsigned int);
#define PMAP_TT_L1_LEVEL 0x1
#define PMAP_TT_L2_LEVEL 0x2
#define PMAP_TT_L3_LEVEL 0x3
#if (__ARM_VMSA__ == 7)
#define PMAP_TT_MAX_LEVEL PMAP_TT_L2_LEVEL
#else
#define PMAP_TT_MAX_LEVEL PMAP_TT_L3_LEVEL
#endif
#ifdef __ARM64_PMAP_SUBPAGE_L1__
#if (__ARM_VMSA__ <= 7)
#error This is not supported for old-style page tables
#endif
#define PMAP_ROOT_ALLOC_SIZE (((ARM_TT_L1_INDEX_MASK >> ARM_TT_L1_SHIFT) + 1) * sizeof(tt_entry_t))
#else
#define PMAP_ROOT_ALLOC_SIZE (ARM_PGBYTES)
#endif
const unsigned int arm_hardware_page_size = ARM_PGBYTES;
const unsigned int arm_pt_desc_size = sizeof(pt_desc_t);
const unsigned int arm_pt_root_size = PMAP_ROOT_ALLOC_SIZE;
#define PMAP_TT_DEALLOCATE_NOBLOCK 0x1
void pmap_init_pte_page_internal(
pmap_t, pt_entry_t *, vm_offset_t, unsigned int , pt_desc_t **);
#if (__ARM_VMSA__ > 7)
static inline tt_entry_t *pmap_tt1e(
pmap_t, vm_map_address_t);
static inline tt_entry_t *pmap_tt2e(
pmap_t, vm_map_address_t);
static inline pt_entry_t *pmap_tt3e(
pmap_t, vm_map_address_t);
static void pmap_unmap_sharedpage32(
pmap_t pmap);
static void pmap_sharedpage_flush_32_to_64(
void);
static boolean_t
pmap_is_64bit(pmap_t);
#endif
static inline tt_entry_t *pmap_tte(
pmap_t, vm_map_address_t);
static inline pt_entry_t *pmap_pte(
pmap_t, vm_map_address_t);
static void pmap_update_cache_attributes_locked(
ppnum_t, unsigned);
boolean_t arm_clear_fast_fault(
ppnum_t ppnum,
vm_prot_t fault_type);