ASIC design of automatic washing machine
Washing machines are everywhere these days. In this projects we will try to implement ASIC design of Aoutomatic washing machine.
Above given image is the state diagram of Aoutomatic washing machine
In a specific automatic washing machine there are usually six states as given above such as, Check door, Fill water, Add detergent, Cycle, Drain water and Spin.
Icarus Verilog or iverilog is an implementation of the Verilog hardware description language.
GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing.
Open your terminal and write following command.
sudo apt update
sudo apt install iverilog
sudo apt install gtkwave
To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
sudo apt install -y git
git clone $ https://github.com/archandesai/iiitb_wm
cd iiitb_wm
iverilog iiitb_wm.v iiitb_wm_tb.v
./a.out
gtkwave iiitb_wm_tb.vcd
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
sudo apt-get update
sudo apt-get -y install yosys
to synthesize
yosys -s yosys_run.sh
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.
Below picture gives an insight of the procedure. Here while using iverilog, you also include gate level verilog models to generate GLS simulation.
Pre - synthesis simulation waveform:
Post - synthesis simulation waveform:
To create custom inverter cell we have to follow following steps
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
cd vsdstdcelldesign
cp ./libs/sky130A.tech sky130A.tech
magic -T sky130A.tech sky130_inv.mag &
This is the layout of the inverter.
For getting physical design we have to do following steps:
- RTL design
- Synthesis
- Floorplanning
- Placement
- Clock tree synthesis
- Routing
- Signoff
- Tapeout
###OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.
First you have to install prerequsites.
apt install -y build-essential python3 python3-venv python3-pip
The docker installation is given here: https://docs.docker.com/engine/install/ubuntu/
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
sudo make
sudo make test
Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow. More about magic at http://opencircuitdesign.com/magic/index.html
Run following commands one by one to fulfill the system requirement.
sudo apt-get install m4
sudo apt-get install tcsh
sudo apt-get install csh
sudo apt-get install libx11-dev
sudo apt-get install tcl-dev tk-dev
sudo apt-get install libcairo2-dev
sudo apt-get install mesa-common-dev libglu1-mesa-dev
sudo apt-get install libncurses-dev
Then we have to do following steps to instal magic.
git clone https://github.com/RTimothyEdwards/magic
cd magic/
sudo make
sudo make install
In this section we will see layout of the projects using openlane and magic for different steps.
To get layout of the project first we have to set few things.
cd OpenLane
cd design
mkdir iiitb_wm
cd iiitb_wm
mkdir src
Here, We have to add config.json file in the iiitb_wm directory. And we have to add following file in src directory : iiitb_wm.v, sky130_fd_sc_hd__fast.lib,sky130_fd_sc_hd__typical.lib,sky130_fd_sc_hd__slow.lib and sky130_vsdinv.lef.
Now we have to do following steps:
cd OpenLane
sudo make mount
./flow.tcl -interactive
package require openlane 0.9
prep -design iiitb_wm
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
In this part we will do sythesis of the project using following code:
run_synthesis
This is synthesized output:
In floorplanning we will do following steps:
run_floorplan
Then we will go to results/floorplan and type following command on terminal
magic -T /home/archan/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/archan/OpenLane/designs/iiitb_wm/runs/RUN_2022.08.30_11.56.04 ../../tmp/merged.nom.lef def read iiitb_wm.def &
We will get following floorplan
In placement we will do following steps:
run_placement
Then we will go to results/placement and type following command on terminal
magic -T /home/archan/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/archan/OpenLane/designs/iiitb_wm/runs/RUN_2022.08.30_11.56.04 ../../tmp/merged.nom.lef def read iiitb_wm.def &
We will get following layout
In this section we wil do following step:
run_cts
We will get following reports after clock tree synthesis
In this step we will do routing of our projects using:
run_routing
Then we will go to results/routing and type following command on terminal
magic -T /home/archan/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/archan/OpenLane/designs/iiitb_wm/runs/RUN_2022.08.30_11.56.04 ../../tmp/merged.nom.lef def read iiitb_wm.def &
We will get following layout after routing.
To get area of the design after rounting we will use box command in magic termina
This is an area of our design.
In this section we will find performance of the design for that we have to follow foloowing step:
cd OpenLane
sudo make mount
sta
read_liberty -max /home/archan/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib
read_liberty -min /home/archan/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib
read_verilog /home/archan/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/iiitb_wm.v
link_design iiitb_wm
read_sdc /home/archan/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/iiitb_wm.sdc
read_spef /home/archan/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/iiitb_wm.spef
set_propagated_clock [all_clocks]
report_checks
report_checks -form _75_ -to _75_
Performance = 1/(data required time - slack)
Performance = 1/(64.83 - 62.05)
Performance = 0.3597 GHz
This is a power analysis of our design.
Flip-flop to standard cell ratio = Flip-flop / Total cell
Flip-flop to standard cell ratio = 3/43
Flip-flop to standard cell ratio = 6.98%
-
Archan Desai
-
Kunal Ghosh
-
Rakshit Bhatia
-
Ishan Desai
-
Arsh Kedia
- Archan Desai, Postgraduate Student, International Institute of Information Technology, Bangalore archan.desai00@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com