xt-q8l-v10-device-tree.patch

diff --git a/arch/arm/dts/rk3288-xt-q8l-v10.dts b/arch/arm/dts/rk3288-xt-q8l-v10.dts
new file mode 100755
index 00000000..be7a0806
--- /dev/null
+++ b/arch/arm/dts/rk3288-xt-q8l-v10.dts
@@ -0,0 +1,749 @@
+/*
+ * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
+ * 					   2018 Paolo Sabatino <paolo.sabatino@gm**l.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "XT-Q8L-V10-RK3288";
+	compatible = "generic,xt-q8l-v10-rk3288", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = &uart2;
+		/*
+		 * We leave this here for future reference, but at the moment
+		 * rk3288 does not support "same-as-spl", instead as a workaround
+		 * we define the boot order statically in:
+		 * board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
+		 *
+		 */
+		u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
+	};
+
+	config {
+		u-boot,dm-spl;
+		u-boot,boot-led = "power";
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cpu0_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000>;
+		};
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp@1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp@1416000000 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1200000>;
+		};
+		opp@1512000000 {
+			opp-hz = /bits/ 64 <1512000000>;
+			opp-microvolt = <1250000>;
+		};
+		opp@1608000000 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1300000>;
+		};
+
+	};
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_key>;
+
+		button@0 {
+			gpio-key,wakeup;
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			label = "GPIO Power";
+			linux,code = <116>;
+			wakeup-source;
+		};
+
+	};
+
+	leds {
+		u-boot,dm-spl;
+		compatible = "gpio-leds";
+
+		power {
+			gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+			u-boot,dm-spl;
+			label = "power";
+			pinctrl-names = "default";
+			pinctrl-0 = <&power_led>;
+		};
+
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_host_5v: usb-host-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_host_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	        regulator-boot-on;
+	        enable-active-high;
+		vin-supply = <&vcc_sys>;
+	};
+
+
+	vcc_otg_5v: usb-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_otg_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vcc_sys>;
+	};
+
+	io_domains {
+		compatible = "rockchip,rk3288-io-voltage-domain";
+		audio-supply = <&vcca_33>;
+		bb-supply = <&vcc_io>;
+		dvp-supply = <&vcc_18>;
+		flash0-supply = <&vcc_flash>;
+		flash1-supply = <&vcc_lan>;
+		gpio30-supply = <&vcc_io>;
+		gpio1830-supply = <&vcc_io>;
+		lcdc-supply = <&vcc_io>;
+		sdcard-supply = <&vccio_sd>;
+		wifi-supply = <&vcc_18>;
+	};
+
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+	operating-points-v2 = <&cpu0_opp_table>;
+	/delete-node/operating-points;
+	/*
+	// Rewrite the operating points table
+	operating-points = <
+		1608000 1350000
+		1512000 1300000
+		1416000 1200000
+		1200000 1100000
+		1008000 1050000
+		 816000 1000000
+		 696000  950000
+		 600000  900000
+	>;
+	*/
+
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_audio {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	vdd_cpu: syr827@40 {
+		compatible = "silergy,syr827";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x40>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x41>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		system-power-controller;
+
+		vp1-supply = <&vcc_sys>;
+		vp2-supply = <&vcc_sys>;
+		vp3-supply = <&vcc_sys>;
+		vp4-supply = <&vcc_sys>;
+		inl1-supply = <&vcc_sys>;
+		inl2-supply = <&vcc_sys>;
+		inl3-supply = <&vcc_20>;
+
+		regulators {
+			vcc_ddr: REG1 {
+				regulator-name = "vcc_ddr";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcc_io: vcc33_lcd: REG2 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_log: REG3 {
+				regulator-name = "vdd_log";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcc_20: REG4 {
+				regulator-name = "vcc_20";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vccio_sd: REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd10_lcd: REG6 {
+				regulator-name = "vdd10_lcd";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcca_18: REG7 {
+				regulator-name = "vcca_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			vcca_33: REG8 {
+				regulator-name = "vcca_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vcc_lan: REG9 {
+				regulator-name = "vcc_lan";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vdd_10: REG10 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vccio_wl: vcc_18: REG11 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vcc18_lcd: REG12 {
+				regulator-name = "vcc18_lcd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&pinctrl {
+
+	u-boot,dm-pre-reloc;
+
+	/*
+		This pin configuration enables the power led and, most important,
+		the power hold pin of the act8846 pmic. Without the power hold
+		bit set, the pmic will shut itself down after a few milliseconds,
+		turning off the whole device. Be aware that in u-boot configuration
+		"pinctrl-names" and "pinctrl-0" properties MUST NOT be stripped
+		away from SPL.
+		Note also that we set the pwr_hold GPIO in board_init_f()
+		function directly in SPL u-boot code which gets executed very soon.
+		The definition here is just a way to be sure that the bit is set
+		again later.
+	*/
+	pinctrl-names = "default";
+	pinctrl-0 = <&power_led>, <&pwr_hold>;
+
+	pcfg_output_high: pcfg-output-high {
+		u-boot,dm-spl;
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	pcfg_wl: pcfg-wl {
+                bias-pull-up;
+                drive-strength = <8>;
+        };
+
+        pcfg_wl_clk: pcfg-wl-clk {
+                bias-disable;
+                drive-strength = <12>;
+        };
+
+	pcfg_wl_int: pcfg-wl-int {
+                bias-pull-up;
+        };
+
+
+	act8846 {
+
+		/*
+		 * Original q8 device tree says:
+		 *  - gpio0 11 HIGH -> power hold
+		 *  - gpio7 1 LOW -> possibly pmic-vsel, we omit it here
+		 */
+		/*pmic_vsel: pmic-vsel {
+			rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+		};*/
+
+		pwr_hold: pwr-hold {
+			rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+	};
+
+	gmac {
+		phy_int: phy-int {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rst: phy-rst {
+			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	hym8563 {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	keys {
+		pwr_key: pwr-key {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+
+		power_led: power-led {
+			rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_host1 {
+
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+    };
+
+	usb_otg {
+
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+&emmc {
+	/*
+	 * eMMC seems to be 52Mhz device on q8 devices, so set it here
+	 * vmmc-supply and vqmmc-supply are removed because they hang
+	 * u-boot >= v2018.03
+	 * From the original q8l firmware and eMMC datasheet it also should
+	 * support DDR highspeed mode, but using mmc-ddr-3_3v or mmc-ddr-1_8v
+	 * properties are not working
+	 */
+	clock-frequency = <50000000>;
+
+	broken-cd;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+
+	status = "okay";
+	u-boot,dm-spl;
+
+};
+
+&sdmmc {
+	bus-width = <4>;
+	supports-sd;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	//vmmc-supply = <&vcc_sd>;
+	//vqmmc-supply = <&vccio_sd>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+/*
+ * Accessible serial port for logging
+ */
+&uart2 {
+	dmas = <&dmac_bus_s 4 &dmac_bus_s 5>;
+	dma-names = "tx", "rx";
+	status = "okay";
+};
+
+/*
+ * Describing resets for usb phy is important because otherwise the USB
+ * port gets stuck in case it goes into autosuspend: plugging any device
+ * when the port is autosuspended will actually kill the port itself and
+ * require a power cycle.
+ * This is required for the usbphy1 phy, nonetheless it is a good idea to
+ * specify the proper resources for all the phys though.
+ * The reference patch which works in conjuction with the reset lines:
+ * https://patchwork.kernel.org/patch/9469811/
+ */
+&usbphy {
+	status = "okay";
+};
+
+&usbphy0 {
+    resets = <&cru SRST_USBOTG_PHY>;
+    reset-names = "phy-reset";
+    vbus-supply = <&vcc_otg_5v>;
+};
+
+&usbphy1 {
+    resets = <&cru SRST_USBHOST0_PHY>;
+    reset-names = "phy-reset";
+};
+
+&usbphy2 {
+    resets = <&cru SRST_USBHOST1_PHY>;
+    reset-names = "phy-reset";
+    vbus-supply = <&vcc_host_5v>;
+};
+
+&usb_host0_ehci {
+    dr_mode = "host";
+    reg = <0x0 0xff500000 0x0 0x20000>;
+    status = "disabled";
+};
+
+/*
+ * Enable the host only USB controller. vbus-supply property allows u-boot
+ * to turn power on for the vbus and allow booting from USB devices
+ */
+&usb_host1 {
+    dr_mode = "host";
+    vbus-supply = <&vcc_host_5v>;
+	status = "okay";
+};
+
+/*
+ * Enable the OTG USB controller. hnp-srp-disable is necessary to allow
+ * it work while in u-boot. Also we attach it to the proper regulator
+ * to enable power during boot phase and allow booting from USB devices
+ */
+&usb_otg {
+	hnp-srp-disable;
+    vbus-supply = <&vcc_otg_5v>;
+	status = "okay";
+};
+
+/*
+ * Disabling vop big because somewhere in some documentation it is stated
+ * that only one vop should be enabled to get video console
+ */
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+/*
+ * xt-q8l-v10 timing registers, dumped directly from a live instance
+ * initialized by the binary rockchip blob.
+ *
+ * pctl-timing are dumped from address 0xff6100c0 to 0xff610144
+ * phy-timing are dumped from address 0xff620030 to 0xff620050
+ * sdram-params are extracted from interconnect, in particular the
+ * service_bus/msch0 part starting at address 0xffac0000 (see section 6.4.2
+ * of the TRM V1.0 manual)
+ */
+&dmc {
+	rockchip,pctl-timing = <0x00000190 0x000000c8 0x00000000 0x00000028
+							0x00000026 0x00000005 0x00000054 0x0002000a
+							0x00000005 0x00000000 0x00000006 0x00000003
+							0x00000011 0x0000001b 0x0000000a 0x00000004
+							0x00000003 0x00000006 0x00000003 0x00000058
+							0x00000003 0x00000000 0x00000024 0x00000000
+							0x00000001 0x00000001 0x00000002 0x00000003
+							0x00000000 0x00000000 0x00000090 0x00000002
+							0x00000006 0x000001f4>;
+	rockchip,phy-timing = <0x3691aa6f 0x185408a0 0x00118c58
+							0x00000000 0x00000083 0x00000004 0x00000001>;
+	/*
+	 * rockchip,sdram-params structure:
+	 *
+	   u32 noc_timing;
+	   u32 noc_activate;
+	   u32 ddrconfig;
+	   u32 ddr_freq;
+	   u32 dramtype;
+		 * DDR Stride is address mapping for DRAM space
+		 * Stride	Ch 0 range	Ch1 range	Total
+		 * 0x00		0-256MB		256MB-512MB	512MB
+		 * 0x05		0-1GB		0-1GB		1GB
+		 * 0x09		0-2GB		0-2GB		2GB
+		 * 0x0d		0-4GB		0-4GB		4GB
+		 * 0x17		N/A		0-4GB		4GB
+		 * 0x1a		0-4GB		4GB-8GB		8GB
+	  u32 stride;
+	  u32 odt;
+
+	 */
+	rockchip,sdram-params = <0x18b1d4db 0x544 0x2 400000000 5 0x9 0>;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&i2c5 {
+	status="okay";
+	u-boot,dm-spl;
+};
+
+&pcfg_pull_up {
+	u-boot,dm-spl;
+};
+