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[WIP] Fix for making the cpu scaling on EspressoBIN working #1304

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merged 4 commits into from May 30, 2019
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@@ -0,0 +1,80 @@
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
index 75491fc84..c2adf380b 100644
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
}

/*
- * Set cpu clock source, for all the level we keep the same
- * clock source that the one already configured. For this one
- * we need to use the clock framework
- */
+ * Set CPU clock source, for all the level we keep the same
+ * clock source that the one already configured with DVS
+ * disabled. For this one we need to use the clock framewor
+ */
parent = clk_get_parent(clk);
+
+ /*
+ * Unset parent clock to force the clock framework setting again
+ * the clock parent
+ */
+ clk_set_parent(clk, NULL);
+
+ /*
+ * For the Armada 37xx CPU clocks, setting the parent will
+ * actually configure the parent when DVFS is enabled. At
+ * hardware level it will be a different register from the one
+ * read when doing clk_get_parent that will be set with
+ * clk_set_parent.
+ */
clk_set_parent(clk, parent);
}

@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
struct armada_37xx_dvfs *dvfs;
struct platform_device *pdev;
unsigned long freq;
- unsigned int cur_frequency;
+ unsigned int cur_frequency, base_frequency;
struct regmap *nb_pm_base, *avs_base;
struct device *cpu_dev;
int load_lvl, ret;
- struct clk *clk;
+ struct clk *clk, *parent;

nb_pm_base =
syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
return PTR_ERR(clk);
}

+ parent = clk_get_parent(clk);
+ if (IS_ERR(parent)) {
+ dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
+ clk_put(clk);
+ return PTR_ERR(parent);
+ }
+
+ /* Get parent CPU frequency */
+ base_frequency = clk_get_rate(parent);
+
+ if (!base_frequency) {
+ dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
+ clk_put(clk);
+ return -EINVAL;
+ }
+
/* Get nominal (current) CPU frequency */
cur_frequency = clk_get_rate(clk);
if (!cur_frequency) {
@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
load_lvl++) {
unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
- freq = cur_frequency / dvfs->divider[load_lvl];
+ freq = base_frequency / dvfs->divider[load_lvl];
ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
if (ret)
goto remove_opp;
@@ -0,0 +1,30 @@
From 80d4cec4cef8282e5ac3aaf98ce3e68fb299a134 Mon Sep 17 00:00:00 2001
From: Terry Zhou <bjzhou@marvell.com>
Date: Mon, 29 Jan 2018 15:01:31 +0800
Subject: [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to SB MPP9

There is an error in the current code that the XTAL MODE
pin was set to SB MPP31 which should be SB MPP9
The latch register of SB MPP9 has different offset of 0x8

Change-Id: I73d41d0c053808fd18944ed1d191aea817b6d21a
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
---
drivers/clk/mvebu/armada-37xx-xtal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c
index 612d65ede10a..5370514959e1 100644
--- a/drivers/clk/mvebu/armada-37xx-xtal.c
+++ b/drivers/clk/mvebu/armada-37xx-xtal.c
@@ -15,8 +15,8 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>

-#define NB_GPIO1_LATCH 0xC
-#define XTAL_MODE BIT(31)
+#define NB_GPIO1_LATCH 0x8
+#define XTAL_MODE BIT(9)

static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
{
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