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| This document describes overlays provided in the kernel packages | |
| For generic Armbian overlays documentation please see | |
| https://docs.armbian.com/User-Guide_Allwinner_overlays/ | |
| ### Platform: | |
| sun7i-a20 (Allwinner A20) | |
| ### Platform details: | |
| Supported pin banks: PB, PC, PD, PE, PG, PH, PI | |
| SPI controller 0 have 2 exposed hardware CS, | |
| other SPI controllers have only one hardware CS | |
| Reference: A20 Datasheet sections 6.3.5.1, 1.19.2 | |
| I2C bus 0 is used for the AXP209 PMIC | |
| ### Provided overlays: | |
| - analog-codec | |
| - can | |
| - i2c1 | |
| - i2c2 | |
| - i2c3 | |
| - i2c4 | |
| - i2s0 | |
| - i2s1 | |
| - mmc2 | |
| - nand | |
| - pps-gpio | |
| - pwm | |
| - spdif-out | |
| - spi0 | |
| - spi1 | |
| - spi2 | |
| - spi-add-cs1 | |
| - spi-jedec-nor | |
| - spi-spidev | |
| - uart1 | |
| - uart2 | |
| - uart3 | |
| - uart4 | |
| - uart5 | |
| - uart6 | |
| - uart7 | |
| - w1-gpio | |
| ### Overlay details: | |
| ### analog-codec | |
| Activates SoC analog codec driver that provides Line Out and Mic In | |
| functionality | |
| ## can | |
| Activates SoC CAN controller | |
| CAN pins (TX, RX): PH20, PH21 | |
| ### i2c1 | |
| Activates TWI/I2C bus 1 | |
| I2C1 pins (SCL, SDA): PB18, PB19 | |
| ### i2c2 | |
| Activates TWI/I2C bus 2 | |
| I2C2 pins (SCL, SDA): PB20, PB21 | |
| ### i2c3 | |
| Activates TWI/I2C bus 3 | |
| I2C3 pins (SCL, SDA): PI0, PI1 | |
| ### i2c4 | |
| Activates TWI/I2C bus 4 | |
| I2C4 pins (SCL, SDA): PI2, PI3 | |
| ### i2s0 | |
| Activates SoC I2S controller 0 | |
| I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12 | |
| ### i2s1 | |
| Activates SoC I2S controller 1 | |
| I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17 | |
| ### mmc2 | |
| Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC | |
| or tSD instead of NAND storage. | |
| MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11 | |
| Parameters: | |
| param_mmc2_cd_pin (pin) | |
| SD/MMC 2 card detect pin | |
| Optional | |
| Default: PH0 | |
| param_mmc2_non_removable (bool) | |
| Option for non-removable storage options on MMC 2 controller (eMMC or tSD) | |
| Optional | |
| Default: 0 | |
| Set to 1 to use this option | |
| ### nand | |
| Activates NAND controller | |
| This overlay should not be used until mainline MLC NAND support | |
| allows using NAND storage reliably | |
| ### pps-gpio | |
| Activates pulse-per-second GPIO client | |
| Parameters: | |
| param_pps_pin (pin) | |
| Pin PPS source is connected to | |
| Optional | |
| Default: PI15 | |
| param_pps_falling_edge (bool) | |
| Assert by falling edge | |
| Optional | |
| Default: 0 | |
| When set (to 1), assert is indicated by a falling edge | |
| (instead of by a rising edge) | |
| ### pwm | |
| Activates hardware PWM controller | |
| PWM pins (PWM0, PWM1): PB2, PI3 | |
| Parameters: | |
| param_pwm_pins (string) | |
| PWM pins activated with this overlay | |
| Optional | |
| Default: both | |
| Supported values: 0, 1, both | |
| If set to 0 only PWM0 can be used, | |
| if set to 1 then only PWM1 can be used, | |
| if set to both (default), both PWM0 and PWM1 can be used | |
| ### spdif-out | |
| Activates SPDIF/Toslink audio output | |
| SPDIF pin: PB13 | |
| ### spi0 | |
| Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it | |
| SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 | |
| ### spi1 | |
| Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it | |
| SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 | |
| ### spi2 | |
| Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it | |
| SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 | |
| SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 | |
| Parameters: | |
| param_spi2_bus_pins (char) | |
| SPI bus 2 pinmux variant | |
| Optional | |
| Default: a | |
| Supported values: a, b | |
| Determines what pins SPI bus 2 is exposed on if SPI 2 is used | |
| ### spi-add-cs1 | |
| Activates SPI chip select 1 on SPI controller 0 | |
| This overlay is required for using chip select 1 with other SPI overlays | |
| SPI 0 CS1 pin: PI14 | |
| ### spi-jedec-nor | |
| Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus | |
| supported by the kernel SPI NOR driver | |
| SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 | |
| SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 | |
| SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 | |
| SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 | |
| Parameters: | |
| param_spinor_spi_bus (int) | |
| SPI bus to activate SPI NOR flash support on | |
| Required | |
| Supported values: 0, 1, 2 | |
| param_spinor_spi_cs (int) | |
| SPI chip select number for SPI NOR connected to SPI bus 0 | |
| Optional | |
| Default: 0 | |
| Supported values: 0, 1 | |
| Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay | |
| param_spinor_max_freq (int) | |
| Maximum SPI frequency | |
| Optional | |
| Default: 1000000 | |
| Range: 3000 - 100000000 | |
| ### spi-spidev | |
| Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, | |
| where X is the bus number and Y is the CS number | |
| SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 | |
| SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 | |
| SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 | |
| SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 | |
| Parameters: | |
| param_spidev_spi_bus (int) | |
| SPI bus to activate mcp2515 support on | |
| Required | |
| Supported values: 0, 1, 2 | |
| param_spidev_spi_cs (int) | |
| SPI chip select number for SPIdev on SPI bus 0 | |
| Optional | |
| Default: 0 | |
| Supported values: 0, 1 | |
| Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay | |
| param_spidev_max_freq (int) | |
| Maximum SPIdev frequency | |
| Optional | |
| Default: 1000000 | |
| Range: 3000 - 100000000 | |
| ### uart2 | |
| Activates serial port 2 (/dev/ttyS2) | |
| UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 | |
| Parameters: | |
| param_uart2_rtscts (bool) | |
| Enable RTS and CTS pins | |
| Optional | |
| Default: 0 | |
| Set to 1 to enable CTS and RTS pins | |
| ### uart3 | |
| Activates serial port 3 (/dev/ttyS3) | |
| UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 | |
| UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 | |
| Parameters: | |
| param_uart3_pins (char) | |
| Determines what pins UART 3 is exposed on | |
| Optional | |
| Default: a | |
| Supported values: a, b | |
| param_uart3_rtscts (bool) | |
| Enable RTS and CTS pins | |
| Optional | |
| Default: 0 | |
| Set to 1 to enable CTS and RTS pins | |
| ### uart4 | |
| Activates serial port 4 (/dev/ttyS4) | |
| UART 4 pins a (TX, RX): PG10, PG11 | |
| UART 4 pins b (TX, RX): PH4, PH5 | |
| Parameters: | |
| param_uart4_pins (char) | |
| Determines what pins UART 4 is exposed on | |
| Optional | |
| Default: a | |
| Supported values: a, b | |
| ### uart 5 | |
| Activates serial port 5 (/dev/ttyS5) | |
| UART 5 pins (TX, RX): PH6, PH7 | |
| ### uart 6 | |
| Activates serial port 6 (/dev/ttyS6) | |
| UART 6 pins (TX, RX): PI12, PI13 | |
| ### uart 7 | |
| Activates serial port 7 (/dev/ttyS7) | |
| UART 7 pins (TX, RX): PI20, PI21 | |
| ### w1-gpio | |
| Activates 1-Wire GPIO master | |
| Requires an external pull-up resistor on the data pin | |
| or enabling the internal pull-up | |
| Parameters: | |
| param_w1_pin (pin) | |
| Data pin for 1-Wire master | |
| Optional | |
| Default: PI15 | |
| param_w1_pin_int_pullup (bool) | |
| Enable internal pull-up for the data pin | |
| Optional | |
| Default: 0 | |
| Set to 1 to enable the pull-up | |
| This option should not be used with multiple sensors or long wires - | |
| please use external pull-up resistor instead |