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README

About
~~~~~
This repo a personal side branch of RISC-V QEMU.

Current status re. riscv/riscv-qemu:

  * alternative TCG frontend:
    * different implementation insn decoder
    * different implementation of certain instructions
    * RVC support
    * missing privileged instructions
  * some nasty linux-user bugs

Linux-user code has been merged into riscv/riscv-qemu.
The parent repo improved their frontend a lot since the time
this branch started, and fixed certain bugs still present here.

Do not use this if you just need a RISC-V qemu.
See https://github.com/riscv/riscv-qemu instead.


Coverage and status
~~~~~~~~~~~~~~~~~~~
User mode RV64/RV32 emulation builds and runs some executables.
System mode emulation is not supported yet.

Extensions A, M, F, D and C are implemented for RV64 and RV32.
Most CSRs are not properly supported, including mandatory counters.
This implementation follows RISC-V ISA spec version 2.1.

GDB remote debugging works.


Building
~~~~~~~~
Follow standard qemu procedure for riscv64-linux-user target:

    ./configure --target-list=riscv64-linux-user [--python=/usr/bin/python2]
    make

Note configure needs explicit python2 command supplied in case the host
python is python 3.x, which is pretty common in modern distros.

Target name for RV32 is riscv32-linux-user.


Debugging
~~~~~~~~~
ISA test suite can be found at https://github.com/arsv/riscv-qemu-tests

Use GDB from the official RISC-V toolchain in extended-remote mode:

    qemu-riscv -g 1234 ./executable

    riscv64-unknown-elf-gdb -ex "target extended-remote :1234" ./executable

Instruction single-stepping, line stepping and breakpoints should work.
GDB should display xN and fN registers properly as well.


Where's the code
~~~~~~~~~~~~~~~~
Check target-riscv/, linux-user/riscv/, and search for TARGET_RISCV ifdefs
in linux-user{main.c,elfload.c,signal.c,syscall_defs.h}.


License and contacts
~~~~~~~~~~~~~~~~~~~~
RISC-V related code in this branch is licensed under the terms
of GNU General Public License version 2, like most of QEMU.

Alex Suykov <alex.suykov@gmail.com>
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