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Stierlitz, the Fearless, Driver-Less Bus Analyzer.
Assembly Verilog Common Lisp
branch: master
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build update README
cypress header
lisp added Stierlitz lisp package and lcd tester.
ml501 update README
tools ready...
LICENSE added makefile
Makefile ready...
block.asm header
debug.asm header
descriptor.asm header
fat16.asm header
hpi.asm header
knobs.asm almost
msc.asm err, 128K image test passed.
payload.asm almost
scsi-cmd.asm header
scsi-data.asm header
scsi-state.asm header
stierlitz.asm err, 128K image test passed.
storage.asm header
usb-bulk.asm header
usbstd.asm err, 128K image test passed.
util.asm header


Got a Xilinx ML501, or another FPGA board with a Cypress CY7C67300 USB controller on it?

Got a bus 31 or fewer bits wide?

Stierlitz will sit on your bus and imitate a USB Mass Storage device.  The latter will appear to have a FAT16 file system on it, containing a single binary "image" file.

Mount it (under Linux, using "mount -o sync ...") and perform arbitrary reads/writes by reading or writing blocks within the image file.

Make sure to use the O_DIRECT flag (or "raw" block device, if your kernel still has it) to disable ALL caching on the PC end.  AFAIK, you cannot do this on Windows or Mac. Therefore I did not bother testing Stierlitz at all on those poor, crippled systems.

If you snip out the FAT16 emulation, you can get 41 bits of address space.

You will need:

1) To build the firmware image, you will need an assembler for the Cypress CY16 architecture: "QTASM.EXE". (Get it here:
2) EZOTGDBG ( to flash the firmware image to the CY7C67300.
3) The Xilinx build tools for your board.  Edit the Makefile in the "ml501" directory, esp. if you have a 32-bit Linux.
4) A UCF file to match your board's wiring, if you have something other than an ML501.
5) (Optional) SBCL ( See the "Lisp" directory.

The "ml501" directory contains a Verilog implementation of the required FPGA-side logic, "stierlitz.v".
If you build using the provided Makefile (edit to insert your Xilinx tool paths) you will have a demo.
The demo gives you a 128K "file" mapped to SRAM ("infer-sram.v"; need an FPGA with at least this much Block RAM to run this.)

Another example, involving an LCD module, can be seen here:
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