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Working timer tick interrupt! Firmware stopwatch application.

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1 parent 7c57dc0 commit 0e44d0f29a2f05ef7f99fb1fc5d670d7f99d7c0b @atgreen committed
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4 cores/MoxieLite/moxielite.vhd
@@ -636,9 +636,9 @@ BEGIN
if gdb_i(1)='0' then
if irq_i='1' then
- if sregfile(0)(1 downto 0)="00" then
+ if sregfile(0)(1 downto 0)="01" then
-- Disable interrupts
- sregfile(0)(0) <= '1';
+ sregfile(0)(0) <= '0';
-- Save the "fault address" in sr5.
sregfile(5) <= PC;
-- Jump to the handler in sr1.
View
15 cores/mpic/mpic.v
@@ -29,19 +29,20 @@ module mpic_wb (/*AUTOARG*/
irq_o <= irq[0] | irq[1] | irq[2] | irq[3] | irq[4];
always @(posedge clk_i)
- irq[0] <= (rst_i | (we & wb_dat_i[0])) ? 1'b0 : irq[0] | irq_i[0];
+ irq[0] <= (rst_i | (we & ~wb_dat_i[0])) ? 1'b0 : irq_i[0] | irq[0];
always @(posedge clk_i)
- irq[1] <= (rst_i | (we & wb_dat_i[1])) ? 1'b0 : irq[1] | irq_i[1];
+ irq[1] <= (rst_i | (we & ~wb_dat_i[1])) ? 1'b0 : irq_i[1] | irq[1];
always @(posedge clk_i)
- irq[2] <= (rst_i | (we & wb_dat_i[2])) ? 1'b0 : irq[2] | irq_i[2];
+ irq[2] <= (rst_i | (we & ~wb_dat_i[2])) ? 1'b0 : irq_i[2] | irq[2];
always @(posedge clk_i)
- irq[3] <= (rst_i | (we & wb_dat_i[3])) ? 1'b0 : irq[3] | irq_i[3];
+ irq[3] <= (rst_i | (we & ~wb_dat_i[3])) ? 1'b0 : irq_i[3] | irq[3];
always @(posedge clk_i)
- irq[4] <= (rst_i | (we & wb_dat_i[4])) ? 1'b0 : irq[4] | irq_i[4];
-
+ irq[4] <= (rst_i | (we & ~wb_dat_i[4])) ? 1'b0 : irq_i[4] | irq[4];
+
+
always @(posedge clk_i)
begin
- wb_ack_o <= wb_stb_i & wb_cyc_i;
+ wb_ack_o <= rst_i ? 1'b0 : wb_stb_i & wb_cyc_i;
end
endmodule // mpic_wb
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3 cores/wishbone/wb_watchdog.v
@@ -53,7 +53,8 @@ module wb_watchdog #(
always @(posedge clk_i) begin
counter <= wbm_stb_i ? 0 : counter + 1;
address <= wbm_stb_i ? wbm_adr_i : address;
- active <= (rst_i | fault_o) ? 1'b0 : wbm_stb_i ? 1'b1 : wbm_ack_i ? 1'b0 : active;
+// active <= (rst_i | fault_o) ? 1'b0 : wbm_stb_i ? 1'b1 : wbm_ack_i ? 1'b0 : active;
+ active <= (rst_i) ? 1'b0 : wbm_stb_i ? 1'b1 : wbm_ack_i ? 1'b0 : active;
end
endmodule // wb_watchdog
View
11 firmware/handler.S
@@ -26,6 +26,8 @@
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.global delay
+
.text
.p2align 1
.global __moxie_exception_handler
@@ -58,13 +60,18 @@ __moxie_exception_handler:
gsr $r0, 5
gsr $r1, 2
gsr $r2, 3
- /* ENABLE INTERRUPTS HERE. */
jsra __handle_exception
/* Insert the return address in our call frame. */
sto.l 4($fp), $r0
-
+
+ /* Re-enable exceptions */
+ ldi.l $r4, 0x1
+ gsr $r3, 0
+ or $r3, $r4
+ ssr $r3, 0
+
mov $r0, $fp
dec $r0, 14*4
mov $sp, $r0
View
13 firmware/marin.S
@@ -7,10 +7,6 @@
.equ BIG_ENDIAN,1
- .equ DISPLAY_ADDR,0x00100000
- .equ UART_ADDR, 0x01000000
-
-
_start:
# Set the top of stack and clear the frame pointer.
ldi.l $sp, _stack
@@ -63,7 +59,6 @@ _exit: jmpa _exit
.global port_7seg_display
.global port_uart
.global port_pic
- .global port_pit
port_7seg_display:
.word 0 # 0x00
@@ -72,9 +67,5 @@ port_uart:
.word 0 # 0x04
.word 0 # 0x06
port_pic:
- .word 0 # 0x08 EnableEdge, Polarity
- .word 0 # 0x0a Mask, Pending
-port_pit:
- .word 0 # 0x0c CNTRL
- .word 0 # 0x0e MOD
- .word 0 # 0x10 CNT
+ .word 0 # 0x08 pending IRQs
+ .word 0 # 0x0a **UNUSED**
View
53 firmware/marin.s
@@ -1,53 +0,0 @@
- .text
- .p2align 1
- .global MarinDisplayTest
- .global main
- .global _exit
- .global __data_start__
- .global __data_end__
- .global __data_load__
-
- .equ BIG_ENDIAN,1
- .equ DISPLAY_ADDR,0x00100000
- .equ UART_ADDR, 0x01000000
-
-
-_start:
-main:
-MarinDisplayTest:
- ldi.l $r1, 72
- sta.b UART_ADDR, $r1
- ldi.l $r1, 69
- sta.b UART_ADDR, $r1
- ldi.l $r1, 76
- sta.b UART_ADDR, $r1
- ldi.l $r1, 76
- sta.b UART_ADDR, $r1
- ldi.l $r1, 79
- sta.b UART_ADDR, $r1
- ldi.l $r1, 33
- sta.b UART_ADDR, $r1
- ldi.l $r1, 0x12345678
- ldi.l $r3, 0x0
-loop: sta.s DISPLAY_ADDR, $r1
- dec $r1, 1
- ldi.l $r2, 50000
-loop2: dec $r2, 1
- cmp $r2, $r3
- bne loop2
- jmpa loop
-
-_exit: jmpa _exit
-
-/* .global __copy_ram
-;; __copy_ram:
-;; ldi.l $r0, 0x5555
-;; sta.s DISPLAY_ADDR, $r0
-;; ldi.l $r0, __data_start__
-;; ldi.l $r1, __data_load__
-;; ldi.l $r2, __data_end__ - __data_start__
-;; jsra memcpy
-;; ret
-
-;; .data
-;; .word 0 */
View
30 firmware/mdata.c
@@ -3,6 +3,7 @@ int bssvalue;
extern volatile short port_7seg_display;
extern volatile short port_uart;
+extern volatile short port_pic;
void delay ()
{
@@ -70,6 +71,9 @@ _read () { return 0; }
/* Called from our asm code. Must return the return address. */
void *__handle_exception (void *faddr, int exc, int code)
{
+ static int c = 0x0;
+ static int q = 0;
+
switch (exc)
{
case MOXIE_EX_DIV0:
@@ -77,20 +81,24 @@ void *__handle_exception (void *faddr, int exc, int code)
/* faddr is the fault address, and div is 2-bytes long, so the
return address is faddr+2. */
return faddr + 2;
- break;
case MOXIE_EX_BAD:
printf("0x%x: ILLEGAL INSTRUCTION EXCEPTION\n", faddr);
return faddr + 2;
- break;
case MOXIE_EX_IRQ:
printf("0x%x: INTERRUPT REQUEST %d\n", faddr, code);
- port_7seg_display = 0x3333;
- while (1);
- break;
+ port_7seg_display = c;
+ q++;
+ if (q == 4)
+ {
+ q = 0;
+ c++;
+ }
+ // Clear the timer interrupt.
+ port_pic = 0;
+ return faddr;
case MOXIE_EX_SWI:
printf("0x%x: SOFTWARE INTERRUPT REQUEST %d\n", faddr, code);
return faddr + 6;
- break;
default:
printf("0x%x: UNKNOWN EXCEPTION 0x%x\n", faddr, exc);
break;
@@ -101,13 +109,17 @@ void __moxie_exception_handler();
int main()
{
- short i = 0;
-
+ short i = 1;
+
+ /* Set the exception handler. */
asm("ssr %0, 1" : : "r" (__moxie_exception_handler));
+ /* Enable interrupts. */
+ asm("ssr %0, 0" : : "r" (i));
+
while (1)
{
- port_7seg_display = i++;
+ // port_7seg_display = i++;
delay ();
}
return 0;
View
4 soc/marin/boards/nexys3/Makefile
@@ -10,7 +10,7 @@ SOURCES = $(wildcard ../../../../cores/MoxieLite/*.vhd) \
$(wildcard ../../../../cores/statled/rtl/*.v) \
$(wildcard ../../../../cores/Nexys3_PSRAM/psram/*.v) \
$(wildcard ../../../../cores/mpic/mpic.v) \
- $(wildcard ../../../../cores/pit/trunk/rtl/verilog/pit_*.v) \
+ $(wildcard ../../../../cores/mtimer/mtimer.v) \
$(wildcard ../../rtl/*.v) \
$(COREGEN_SOURCES)
@@ -41,7 +41,7 @@ bootrom.vh: $(BOOTROM_SOURCES) ../../moxie-marin.ld
moxie-elf-gcc $(CFLAGS) marin.o mdata.o handler.o -o bootrom.elf -T../../moxie-marin.ld -lnosys
# moxie-elf-objcopy -O verilog bootrom.elf bootrom.vh
data2mem -bd bootrom.elf -d -o m bootrom.mem
- mv bootrom.mem bootrom.vh
+ grep -v @ bootrom.mem > bootrom.vh
$(PROJECT).prj: bootrom.vh ../../../../cores/gdbtarget/messages.vh $(SOURCES)
rm -f $(PROJECT).prj
View
6 soc/marin/boards/nexys3/Nexys3_Master.ucf
@@ -192,4 +192,10 @@ Net "an<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1D
# NET "mem_data[15]" IOSTANDARD = LVCMOS33;
# NET "mem_data[15]" LOC = T8;
+# Buttons
+Net "btns" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS
+Net "btnu" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU
Net "btnl" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL
+Net "btnd" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND
+Net "btnr" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR
+
View
54 soc/marin/rtl/marin.v
@@ -22,17 +22,16 @@ module marin (/*AUTOARG*/
// Outputs
seg, an, tx_o, leds_o,
// Inputs
- rst_i, clk_100mhz_i, btnl, rx_i
+ rst_i, clk_100mhz_i, btnl, btnr, btnu, btnd, btns, rx_i
);
// --- Clock and Reset ------------------------------------------
input rst_i, clk_100mhz_i;
reg rst;
- input btnl;
+ input btnl, btnr, btnu, btnd, btns;
-
- // -- Seven Segment Display -------------------------------------
+ // -- Seven Segment Display -------------------------------------
output [7:0] seg;
output [3:0] an;
@@ -128,15 +127,7 @@ module marin (/*AUTOARG*/
wire wb2pi_stb;
wire pi2wb_ack;
- // Programmable timer
- wire [15:0] wb2ti_dat;
- wire [15:0] ti2wb_dat;
- wire [31:0] wb2ti_adr;
- wire [1:0] wb2ti_sel;
- wire wb2ti_we;
- wire wb2ti_cyc;
- wire wb2ti_stb;
- wire ti2wb_ack;
+ wire ti2pi_irq;
wire clk_cpu;
wire clk_100mhz;
@@ -230,16 +221,7 @@ module marin (/*AUTOARG*/
.wbs_5_we_o (wb2pi_we),
.wbs_5_cyc_o (wb2pi_cyc),
.wbs_5_stb_o (wb2pi_stb),
- .wbs_5_ack_i (pi2wb_ack),
-
- .wbs_6_dat_o (wb2ti_dat),
- .wbs_6_dat_i (ti2wb_dat),
- .wbs_6_adr_o (wb2ti_adr),
- .wbs_6_sel_o (wb2ti_sel),
- .wbs_6_we_o (wb2ti_we),
- .wbs_6_cyc_o (wb2ti_cyc),
- .wbs_6_stb_o (wb2ti_stb),
- .wbs_6_ack_i (ti2wb_ack));
+ .wbs_5_ack_i (pi2wb_ack));
wire br_debug;
wire [7:0] ml_debug;
@@ -286,7 +268,7 @@ module marin (/*AUTOARG*/
.wb_ack_o (pi2wb_ack),
.wb_dat_o (pi2wb_dat),
.irq_o (pi2mx_irq),
- .irq_i ({4'b0, btnl}));
+ .irq_i ({btnl, btnr, btnu, btnd, ti2pi_irq}));
// psram_wb cellram (.clk_i (clk_cpu),
// // Wishbone Interface
@@ -311,24 +293,10 @@ module marin (/*AUTOARG*/
// .mem_data_o (mem_data_o),
// .mem_data_t (mem_data));
- wire ti_pit;
- wire ti_pit_irq;
+ mtimer tick_generator (.clk_i (clk_cpu),
+ .rst_i (rst_i),
+ .tick_o (ti2pi_irq));
- pit_top #(.DWIDTH (16)) pit
- (.wb_dat_o (ti2wb_dat),
- .wb_ack_o (ti2wb_ack),
- .wb_clk_i (clk_cpu),
- .wb_rst_i (rst_i),
- .arst_i (1'b0),
- .wb_adr_i (wb2ti_adr[2:0]),
- .wb_dat_i (wb2ti_dat),
- .wb_we_i (wb2ti_we),
- .wb_stb_i (wb2ti_stb),
- .wb_cyc_i (wb2ti_cyc),
- .wb_sel_i (wb2ti_sel),
- .pit_o (ti_pit),
- .pit_irq_o (ti_pit_irq));
-
wire [12:0] gdbdebug;
nexys7seg_wb disp (.rst_i (rst_i),
@@ -394,6 +362,8 @@ module marin (/*AUTOARG*/
.tx_o (tx_o),
.gdb_ctrl_o (gdb2mx));
- assign leds_o = ml_debug;
+ assign leds_o = {watchdog_adr[7:0]};
+
+// ml_debug[6:0]};
endmodule

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