Permalink
Browse files

Define and use microcoded pipeline control signals

  • Loading branch information...
1 parent 227d8c9 commit 5058282af07d60188e31cd7484693fecf5383cda @atgreen committed Jun 23, 2012
Oops, something went wrong.
Oops, something went wrong.
@@ -18,41 +18,40 @@
// 02110-1301, USA.
module cpu_write (/*AUTOARG*/
- // Outputs
- register_write_index_o, register_we_o, reg_result_o,
- // Inputs
- rst_i, clk_i, register_write_index_i, register_we_i, memory_we_i,
- loadp_i, memory_address_i, reg_result_i, mem_result_i
- );
+ // Outputs
+ register_write_index_o, register_we_o, reg_result_o,
+ // Inputs
+ rst_i, clk_i, pipeline_control_bits_i, register_write_index_i,
+ memory_address_i, reg_result_i, mem_result_i
+ );
// --- Clock and Reset ------------------------------------------
input rst_i, clk_i;
+ input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
input [3:0] register_write_index_i;
- input [0:0] register_we_i;
- input [0:0] memory_we_i;
- input [0:0] loadp_i;
input [31:0] memory_address_i;
input [31:0] reg_result_i;
input [31:0] mem_result_i;
+
output [3:0] register_write_index_o;
output [0:0] register_we_o;
output [31:0] reg_result_o;
wire [31:0] data;
wire [3:0] register_write_index_o = register_write_index_i;
- wire [0:0] register_we_o = register_we_i;
+ wire [0:0] register_we_o = pipeline_control_bits_i[`PCB_WR];
- // loadp_i is high if we are loading memory from cache
- wire [31:0] reg_result_o = loadp_i ? data : reg_result_i;
+ // PCB_RM is high if we are loading memory from cache
+ wire [31:0] reg_result_o = pipeline_control_bits_i[`PCB_RM] ? data : reg_result_i;
// The data cache. Fake. Never stalls. Note that we can do a single
// cycle memory-to-memory transfer.
dcache cache (.clk_i (clk_i),
.rst_i (rst_i),
- .we_i (memory_we_i),
+ .we_i (pipeline_control_bits_i[`PCB_WM]),
.address_i (memory_address_i),
.data_i (mem_result_i),
.data_o (data));
@@ -17,6 +17,13 @@
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
// 02110-1301, USA.
+`define PCB_WIDTH 5
+`define PCB_WR 4
+`define PCB_RA 3
+`define PCB_RB 2
+`define PCB_WM 1
+`define PCB_RM 0
+
`define OP_ADD_L 6'b000000
`define OP_AND 6'b000001
`define OP_ASHL 6'b000010
@@ -3,62 +3,64 @@ Form 1 Instruction Microcode
name - instruction name
code - form 1 opcode value
-w reg? - writes to register A?
-r A? - reads register A?
-r B? - reads register B?
+wr? - writes to register A?
+rA? - reads register A?
+rB? - reads register B?
+wm? - writes to memory?
+rm? - reads from memory?
notes - misc. comments
-|--------+----------+--------+------+------+-------|
-| name | code | w reg? | r A? | r B? | notes |
-|--------+----------+--------+------+------+-------|
-| nop | 00000000 | 0 | 0 | 0 | |
-| ldi.l | 00000001 | 1 | 0 | 0 | |
-| mov | 00000010 | 1 | 0 | 1 | |
-| jsra | 00000011 | 0 | 0 | 0 | |
-| ret | 00000100 | 0 | 0 | 0 | |
-| add.l | 00000101 | 1 | 1 | 1 | |
-| push | 00000110 | 0 | 0 | 0 | |
-| pop | 00000111 | 0 | 0 | 0 | |
-| lda.l | 00001000 | 1 | 0 | 0 | |
-| sta.l | 00001001 | 0 | 1 | 0 | |
-| ld.l | 00001010 | 1 | 1 | 0 | |
-| st.l | 00001011 | 0 | 1 | 0 | |
-| ldo.l | 00001100 | 1 | 1 | 1 | |
-| sto.l | 00001101 | 0 | 1 | 1 | |
-| cmp | 00001110 | 0 | 1 | 1 | |
-| jsr | 00011001 | 0 | 1 | 0 | |
-| jmpa | 00011010 | 0 | 0 | 0 | |
-| ldi.b | 00011011 | 1 | 0 | 0 | |
-| ld.b | 00011100 | 1 | 1 | 0 | |
-| lda.b | 00011101 | 1 | 0 | 0 | |
-| st.b | 00011110 | 0 | 1 | 1 | |
-| sta.b | 00011111 | 0 | 1 | 0 | |
-| ldi.s | 00100000 | 1 | 0 | 0 | |
-| ld.s | 00100001 | 1 | 1 | 0 | |
-| lda.s | 00100010 | 1 | 1 | 0 | |
-| st.s | 00100011 | 0 | 1 | 1 | |
-| sta.s | 00100100 | 0 | 1 | 0 | |
-| jmp | 00100101 | 0 | 0 | 0 | |
-| and | 00100110 | 1 | 1 | 1 | |
-| lshr | 00100111 | 1 | 1 | 1 | |
-| ashr | 00101000 | 1 | 1 | 1 | |
-| sub.l | 00101001 | 1 | 1 | 1 | |
-| neg | 00101010 | 1 | 1 | 1 | |
-| or | 00101011 | 1 | 1 | 1 | |
-| not | 00101100 | 1 | 1 | 1 | |
-| ashr | 00101101 | 1 | 1 | 1 | |
-| xor | 00101110 | 1 | 1 | 1 | |
-| mul.l | 00101111 | 1 | 1 | 1 | |
-| swi | 00110000 | 0 | 0 | 0 | |
-| div.l | 00110001 | 1 | 1 | 1 | |
-| udiv.l | 00110010 | 1 | 1 | 1 | |
-| mod.l | 00110011 | 1 | 1 | 1 | |
-| umod.l | 00110100 | 1 | 1 | 1 | |
-| brk | 00110101 | 0 | 0 | 0 | |
-| ldo.b | 00110110 | 1 | 1 | 1 | |
-| sto.b | 00110111 | 0 | 1 | 1 | |
-| ldo.s | 00111000 | 1 | 1 | 1 | |
-| sto.s | 00111001 | 0 | 0 | 0 | |
-|--------+----------+--------+------+------+-------|
+|--------+----------+-----+-----+-----+-----+-----+-------|
+| name | code | wr? | rA? | rB? | wm? | rm? | notes |
+|--------+----------+-----+-----+-----+-----+-----+-------|
+| nop | 00000000 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.l | 00000001 | 1 | 0 | 0 | 0 | 0 | |
+| mov | 00000010 | 1 | 0 | 1 | 0 | 0 | |
+| jsra | 00000011 | 0 | 0 | 0 | 0 | 0 | |
+| ret | 00000100 | 0 | 0 | 0 | 0 | 0 | |
+| add.l | 00000101 | 1 | 1 | 1 | 0 | 0 | |
+| push | 00000110 | 0 | 0 | 0 | 0 | 0 | |
+| pop | 00000111 | 0 | 0 | 0 | 0 | 0 | |
+| lda.l | 00001000 | 1 | 0 | 0 | 0 | 1 | |
+| sta.l | 00001001 | 0 | 1 | 0 | 1 | 0 | |
+| ld.l | 00001010 | 1 | 1 | 0 | 0 | 1 | |
+| st.l | 00001011 | 0 | 1 | 0 | 1 | 0 | |
+| ldo.l | 00001100 | 1 | 1 | 1 | 0 | 1 | |
+| sto.l | 00001101 | 0 | 1 | 1 | 1 | 0 | |
+| cmp | 00001110 | 0 | 1 | 1 | 0 | 0 | |
+| jsr | 00011001 | 0 | 1 | 0 | 0 | 0 | |
+| jmpa | 00011010 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.b | 00011011 | 1 | 0 | 0 | 0 | 0 | |
+| ld.b | 00011100 | 1 | 1 | 0 | 0 | 1 | |
+| lda.b | 00011101 | 1 | 0 | 0 | 0 | 1 | |
+| st.b | 00011110 | 0 | 1 | 1 | 1 | 0 | |
+| sta.b | 00011111 | 0 | 1 | 0 | 1 | 0 | |
+| ldi.s | 00100000 | 1 | 0 | 0 | 0 | 0 | |
+| ld.s | 00100001 | 1 | 1 | 0 | 0 | 1 | |
+| lda.s | 00100010 | 1 | 1 | 0 | 0 | 1 | |
+| st.s | 00100011 | 0 | 1 | 1 | 1 | 0 | |
+| sta.s | 00100100 | 0 | 1 | 0 | 1 | 0 | |
+| jmp | 00100101 | 0 | 0 | 0 | 0 | 0 | |
+| and | 00100110 | 1 | 1 | 1 | 0 | 0 | |
+| lshr | 00100111 | 1 | 1 | 1 | 0 | 0 | |
+| ashr | 00101000 | 1 | 1 | 1 | 0 | 0 | |
+| sub.l | 00101001 | 1 | 1 | 1 | 0 | 0 | |
+| neg | 00101010 | 1 | 1 | 1 | 0 | 0 | |
+| or | 00101011 | 1 | 1 | 1 | 0 | 0 | |
+| not | 00101100 | 1 | 1 | 1 | 0 | 0 | |
+| ashr | 00101101 | 1 | 1 | 1 | 0 | 0 | |
+| xor | 00101110 | 1 | 1 | 1 | 0 | 0 | |
+| mul.l | 00101111 | 1 | 1 | 1 | 0 | 0 | |
+| swi | 00110000 | 0 | 0 | 0 | 0 | 0 | |
+| div.l | 00110001 | 1 | 1 | 1 | 0 | 0 | |
+| udiv.l | 00110010 | 1 | 1 | 1 | 0 | 0 | |
+| mod.l | 00110011 | 1 | 1 | 1 | 0 | 0 | |
+| umod.l | 00110100 | 1 | 1 | 1 | 0 | 0 | |
+| brk | 00110101 | 0 | 0 | 0 | 0 | 0 | |
+| ldo.b | 00110110 | 1 | 1 | 1 | 0 | 1 | |
+| sto.b | 00110111 | 0 | 1 | 1 | 1 | 0 | |
+| ldo.s | 00111000 | 1 | 1 | 1 | 0 | 1 | |
+| sto.s | 00111001 | 0 | 0 | 0 | 1 | 0 | |
+|--------+----------+-----+-----+-----+-----+-----+-------|
@@ -27,16 +27,16 @@ module microcode (/*AUTOARG*/
);
input [7:0] opcode;
- output [2:0] q;
+ output [`PCB_WIDTH-1:0] q;
- reg [2:0] rom[0:63];
+ reg [`PCB_WIDTH-1:0] rom[0:63];
initial $readmemb("microcode.bin", rom);
- wire [2:0] f1, f2;
+ wire [`PCB_WIDTH-1:0] f1, f2;
assign f1 = rom[opcode[5:0]];
- assign f2 = 3'b111;
+ assign f2 = 5'b11111;
assign q = (opcode[7] ? f2 : f1);
@@ -64,11 +64,9 @@ module moxie (/*AUTOARG*/
wire [0:0] fd_valid;
wire [31:0] dx_operand;
wire [31:0] dx_PC;
- wire [0:0] dx_register_write_enable;
+ wire [`PCB_WIDTH-1:0] dx_pipeline_control_bits;
wire [5:0] dx_op;
- wire [0:0] xw_register_write_enable;
- wire [0:0] xw_loadp;
- wire [0:0] xw_memory_we;
+ wire [`PCB_WIDTH-1:0] xw_pipeline_control_bits;
wire [0:0] wr_register_write_enable;
wire [3:0] dx_register_write_index;
wire [3:0] xw_register_write_index;
@@ -90,10 +88,8 @@ module moxie (/*AUTOARG*/
wire [31:0] rx_reg_value1;
wire [31:0] rx_reg_value2;
- wire [3:0] dx_reg_index1;
- wire [3:0] dx_reg_index2;
- wire [3:0] xr_reg_index1;
- wire [3:0] xr_reg_index2;
+ wire [3:0] dr_reg_index1;
+ wire [3:0] dr_reg_index2;
wire [0:0] stall_x;
@@ -125,8 +121,8 @@ module moxie (/*AUTOARG*/
.write_enable0_i (wr_register_write_enable),
.write_enable1_i (0),
.reg_write_index0_i (wr_register_write_index),
- .reg_read_index0_i (xr_reg_index1),
- .reg_read_index1_i (xr_reg_index2),
+ .reg_read_index0_i (dr_reg_index1),
+ .reg_read_index1_i (dr_reg_index2),
.sp_o (rx_sp),
.fp_o (rx_fp),
.value0_i (wr_reg_result),
@@ -167,12 +163,12 @@ module moxie (/*AUTOARG*/
.valid_i (fd_valid),
.stall_i (hazard_war | stall_x),
// Outputs
- .register_write_enable_o (dx_register_write_enable),
+ .pipeline_control_bits_o (dx_pipeline_control_bits),
.register_write_index_o (dx_register_write_index),
.operand_o (dx_operand),
.PC_o (dx_PC),
- .riA_o (dx_reg_index1),
- .riB_o (dx_reg_index2),
+ .riA_o (dr_reg_index1),
+ .riB_o (dr_reg_index2),
.op_o (dx_op));
cpu_execute stage_execute (// Inputs
@@ -183,33 +179,26 @@ module moxie (/*AUTOARG*/
.op_i (dx_op),
.PC_i (dx_PC),
.operand_i (dx_operand[31:0]),
- .riA_i (dx_reg_index1),
- .riB_i (dx_reg_index2),
- .riA_o (xr_reg_index1),
- .riB_o (xr_reg_index2),
.regA_i (rx_reg_value1),
.regB_i (rx_reg_value2),
.branch_flag_o (xf_branch_flag),
.branch_target_o (xf_branch_target),
+ .pipeline_control_bits_i (dx_pipeline_control_bits),
.register_write_index_i (dx_register_write_index),
// Outputs
- .register_write_enable_o (xw_register_write_enable),
+ .pipeline_control_bits_o (xw_pipeline_control_bits),
.register_write_index_o (xw_register_write_index),
.reg_result_o (xw_reg_result),
.mem_result_o (xw_mem_result),
.memory_address_o (xw_memory_address),
- .memory_read_enable_o (xw_loadp),
- .memory_write_enable_o (xw_memory_we),
.sp_i (rx_sp),
.fp_i (rx_fp));
cpu_write stage_write ( // Inputs
.rst_i (rst_i),
.clk_i (clk_i),
.register_write_index_i (xw_register_write_index),
- .register_we_i (xw_register_write_enable),
- .loadp_i (xw_loadp),
- .memory_we_i (xw_memory_we),
+ .pipeline_control_bits_i (xw_pipeline_control_bits),
.memory_address_i (xw_memory_address),
.reg_result_i (xw_reg_result),
.mem_result_i (xw_mem_result),
@@ -218,8 +207,15 @@ module moxie (/*AUTOARG*/
.register_we_o (wr_register_write_enable),
.reg_result_o (wr_reg_result));
- assign hazard_war = xw_register_write_enable
- & ((xw_register_write_index == dx_reg_index1)
- | (xw_register_write_index == dx_reg_index2));
-
+ assign hazard_war = 0;
+
+
+ // assign hazard_war = dx_pipeline_control_bits[`PCB_RB] &
+ // xw_pipeline_control_bits[`PCB_WR] &
+ // xw_register_write_index == dx_reg_index2;
+
+ // assign hazard_war = (xw_pipeline_control_bits[`PCB_WR]
+ // & ((xw_register_write_index == dx_reg_index1)
+ // | (xw_register_write_index == dx_reg_index2)));
+
endmodule // moxie
@@ -36,7 +36,7 @@
(loop for filepos = (file-position in)
for line = (read-line in nil)
until (let ((s (cl-ppcre:split "\\|" line)))
- (equal (length s) 7)))
+ (equal (length s) 9)))
(read-line in nil)
;; We're at the table contents now. Parse it and write our new
@@ -48,11 +48,11 @@
for line = (read-line in nil)
while line do
(let ((s (cl-ppcre:split "\\|" line)))
- (if (equal 7 (length s))
- (destructuring-bind (junk1 name code wreg? rA? rb? &rest junk2)
+ (if (equal 9 (length s))
+ (destructuring-bind (junk1 name code wr? rA? rB? rm? wm? &rest junk2)
(mapcar (lambda (v) (string-trim " " v)) s)
(setf (aref opcode-array (parse-integer code :radix 2))
- (list name wreg? rA? rb?))))))
+ (list name wr? rA? rB? rm? wm?))))))
(loop for i from 0 to 63
do (let ((o (aref opcode-array i)))
(if o
@@ -63,7 +63,7 @@
((equal n 1) (format out "1"))
(t (error "bad table entry")))))
(cdr o))
- (format out "000"))
+ (format out "00000"))
(format out "~%"))))
(close in)))

0 comments on commit 5058282

Please sign in to comment.