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Define and use microcoded pipeline control signals

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commit 5058282af07d60188e31cd7484693fecf5383cda 1 parent 227d8c9
@atgreen authored
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810 moxie/cores/moxie/cpu_decode.v
@@ -21,418 +21,422 @@
module cpu_decode (/*AUTOARG*/
// Outputs
- register_write_enable_o, register_write_index_o, operand_o, riA_o,
- riB_o, op_o, PC_o,
+ pipeline_control_bits_o, register_write_index_o, operand_o, riAr_o,
+ riBr_o, riA_o, riB_o, op_o, PC_o,
// Inputs
rst_i, clk_i, stall_i, opcode_i, operand_i, valid_i, PC_i
);
- // --- Clock and Reset ------------------------------------------
- input rst_i, clk_i;
+ // --- Clock and Reset ------------------------------------------
+ input rst_i, clk_i;
- // --- Pipeline interlock ---------------------------------------
- input stall_i;
-
- // --- Instructions ---------------------------------------------
- input [15:0] opcode_i;
- input [31:0] operand_i;
- input valid_i;
- input [31:0] PC_i;
-
- // --- Outputs --------------------------------------------------
- output [0:0] register_write_enable_o;
- output [3:0] register_write_index_o;
- output [31:0] operand_o;
- output [3:0] riA_o;
- output [3:0] riB_o;
- output [5:0] op_o;
- output [31:0] PC_o;
+ // --- Pipeline interlock ---------------------------------------
+ input stall_i;
+
+ // --- Instructions ---------------------------------------------
+ input [15:0] opcode_i;
+ input [31:0] operand_i;
+ input valid_i;
+ input [31:0] PC_i;
+
+ // --- Outputs --------------------------------------------------
+ output [`PCB_WIDTH-1:0] pipeline_control_bits_o;
+ output [3:0] register_write_index_o;
+ output [31:0] operand_o;
+ output [3:0] riAr_o;
+ output [3:0] riBr_o;
+ output [3:0] riA_o;
+ output [3:0] riB_o;
+ output [5:0] op_o;
+ output [31:0] PC_o;
- reg [5:0] op_o;
- wire [3:0] riA;
- wire [3:0] riB;
- reg [3:0] riA_o;
- reg [3:0] riB_o;
- reg [31:0] operand_o;
- reg [31:0] PC_o;
- reg [0:0] register_write_enable_o;
- reg [3:0] register_write_index_o;
+ reg [5:0] op_o;
+ wire [3:0] riA_o;
+ wire [3:0] riB_o;
+ reg [3:0] riAr_o;
+ reg [3:0] riBr_o;
+ reg [31:0] operand_o;
+ reg [31:0] PC_o;
+ reg [`PCB_WIDTH-1:0] pipeline_control_bits_o;
+ reg [3:0] register_write_index_o;
- wire foo = !opcode_i[15:15];
- wire [3:0] b1 = opcode_i[3:0];
- wire [3:0] b2 = opcode_i[7:4];
- wire [3:0] b3 = opcode_i[11:8];
- wire [3:0] b4 = opcode_i[15:12];
+ wire foo = !opcode_i[15:15];
+ wire [3:0] b1 = opcode_i[3:0];
+ wire [3:0] b2 = opcode_i[7:4];
+ wire [3:0] b3 = opcode_i[11:8];
+ wire [3:0] b4 = opcode_i[15:12];
- wire [2:0] control;
+ wire [`PCB_WIDTH-1:0] control;
- microcode mcode (.opcode(opcode_i[15:8]),
- .q(control));
+ microcode mcode (.opcode(opcode_i[15:8]),
+ .q(control));
- assign riA = foo ? opcode_i[7:4] : opcode_i[11:8];
- assign riB = opcode_i[3:0];
+ assign riA_o = foo ? opcode_i[7:4] : opcode_i[11:8];
+ assign riB_o = opcode_i[3:0];
- always @(posedge clk_i)
- begin
- riA_o <= riA;
- riB_o <= riB;
- PC_o <= PC_i;
- end
-
- always @(posedge clk_i)
- begin
- register_write_enable_o <= control[2];
- if (stall_i | !valid_i)
- begin
- op_o <= `OP_NOP;
- end
- else begin
- register_write_index_o <= riA;
- casex (opcode_i[15:8])
- 8'b00000000:
- begin
- op_o <= `OP_NOP;
- end
- 8'b00000001:
- begin
- op_o <= `OP_LDI_L;
- operand_o <= operand_i;
- end
- 8'b00000010:
- begin
- op_o <= `OP_MOV;
- end
- 8'b00000011:
- begin
- op_o <= `OP_JSRA;
- end
- 8'b00000100:
- begin
- op_o <= `OP_RET;
- end
- 8'b00000101:
- begin
- op_o <= `OP_ADD_L;
- end
- 8'b00000110:
- begin
- op_o <= `OP_PUSH;
- end
- 8'b00000111:
- begin
- op_o <= `OP_POP;
- end
- 8'b00001000:
- begin
- op_o <= `OP_LDA_L;
- operand_o <= operand_i;
- end
- 8'b00001001:
- begin
- op_o <= `OP_STA_L;
- operand_o <= operand_i;
- end
- 8'b00001010:
- begin
- op_o <= `OP_LD_L;
- end
- 8'b00001011:
- begin
- op_o <= `OP_ST_L;
- end
- 8'b00001100:
- begin
- op_o <= `OP_LDO_L;
- end
- 8'b00001101:
- begin
- op_o <= `OP_STO_L;
- end
- 8'b00001110:
- begin
- op_o <= `OP_CMP;
- end
- 8'b00001111:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010000:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010001:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010010:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010011:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010100:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010101:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010110:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00010111:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00011000:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00011001:
- begin
- op_o <= `OP_JSR;
- end
- 8'b00011010:
- begin
- op_o <= `OP_JMPA;
- operand_o <= operand_i;
- end
- 8'b00011011:
- begin
- op_o <= `OP_LDI_B;
- end
- 8'b00011100:
- begin
- op_o <= `OP_LD_B;
- end
- 8'b00011101:
- begin
- op_o <= `OP_LDA_B;
- end
- 8'b00011110:
- begin
- op_o <= `OP_ST_B;
- end
- 8'b00011111:
- begin
- op_o <= `OP_STA_B;
- end
- 8'b00100000:
- begin
- op_o <= `OP_LDI_S;
- end
- 8'b00100001:
- begin
- op_o <= `OP_LD_S;
- end
- 8'b00100010:
- begin
- op_o <= `OP_LDA_S;
- end
- 8'b00100011:
- begin
- op_o <= `OP_ST_S;
- end
- 8'b00100100:
- begin
- op_o <= `OP_STA_S;
- end
- 8'b00100101:
- begin
- op_o <= `OP_JMP;
- end
- 8'b00100110:
- begin
- op_o <= `OP_AND;
- end
- 8'b00100111:
- begin
- op_o <= `OP_LSHR;
- end
- 8'b00101000:
- begin
- op_o <= `OP_ASHL;
- end
- 8'b00101001:
- begin
- op_o <= `OP_SUB_L;
- end
- 8'b00101010:
- begin
- op_o <= `OP_NEG;
- end
- 8'b00101011:
- begin
- op_o <= `OP_OR;
- end
- 8'b00101100:
- begin
- op_o <= `OP_NOT;
- end
- 8'b00101101:
- begin
- op_o <= `OP_ASHR;
- end
- 8'b00101110:
- begin
- op_o <= `OP_XOR;
- end
- 8'b00101111:
- begin
- op_o <= `OP_MUL_L;
- end
- 8'b00110000:
- begin
- op_o <= `OP_SWI;
- end
- 8'b00110001:
- begin
- op_o <= `OP_DIV_L;
- end
- 8'b00110010:
- begin
- op_o <= `OP_UDIV_L;
- end
- 8'b00110011:
- begin
- op_o <= `OP_MOD_L;
- end
- 8'b00110100:
- begin
- op_o <= `OP_UMOD_L;
- end
- 8'b00110101:
- begin
- op_o <= `OP_BRK;
- end
- 8'b00110110:
- begin
- op_o <= `OP_LDO_B;
- end
- 8'b00110111:
- begin
- op_o <= `OP_STO_B;
- end
- 8'b00111000:
- begin
- op_o <= `OP_LDO_S;
- end
- 8'b00111001:
- begin
- op_o <= `OP_STO_S;
- end
- 8'b00111010:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00111011:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00111100:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00111101:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00111110:
- begin
- op_o <= `OP_BAD;
- end
- 8'b00111111:
- begin
- op_o <= `OP_BAD;
- end
- 8'b1000????:
- begin
- op_o <= `OP_INC;
- operand_o <= opcode_i[3:0];
- end
- 8'b1001????:
- begin
- op_o <= `OP_DEC;
- operand_o <= opcode_i[3:0];
- end
- 8'b1010????:
- begin
- op_o <= `OP_GSR;
- end
- 8'b1011????:
- begin
- op_o <= `OP_SSR;
- end
- 8'b110000??:
- begin
- op_o <= `OP_BEQ;
- end
- 8'b110001??:
- begin
- op_o <= `OP_BNE;
- end
- 8'b110010??:
- begin
- op_o <= `OP_BLT;
- end
- 8'b110011??:
- begin
- op_o <= `OP_BGT;
- end
- 8'b110100??:
- begin
- op_o <= `OP_BLTU;
- end
- 8'b110101??:
- begin
- op_o <= `OP_BGTU;
- end
- 8'b110110??:
- begin
- op_o <= `OP_BGE;
- end
- 8'b110111??:
- begin
- op_o <= `OP_BLE;
- end
- 8'b111000??:
- begin
- op_o <= `OP_BGEU;
- end
- 8'b111001??:
- begin
- op_o <= `OP_BLEU;
- end
- 8'b111010??:
- begin
- op_o <= `OP_BAD;
- end
- 8'b111011??:
- begin
- op_o <= `OP_BAD;
- end
- 8'b111100??:
- begin
- op_o <= `OP_BAD;
- end
- 8'b111101??:
- begin
- op_o <= `OP_BAD;
- end
- 8'b111110??:
- begin
- op_o <= `OP_BAD;
- end
- 8'b111111??:
- begin
- op_o <= `OP_BAD;
- end
- endcase // casex (opcode_i)
- // register_write_enable_o <= (!op_nop) & (op_ldi|op_dec|op_xor|op_sub);
- end // if (! rst_i && ! stall_i)
- end
+ always @(posedge clk_i)
+ begin
+ if (! stall_i) begin
+ riAr_o <= riA_o;
+ riBr_o <= riB_o;
+ PC_o <= PC_i;
+ end
+ end
+
+ always @(posedge clk_i)
+ begin
+ if (! stall_i) begin
+ pipeline_control_bits_o <= control;
+ if (!valid_i)
+ op_o <= `OP_NOP;
+ else begin
+ register_write_index_o <= riA_o;
+ casex (opcode_i[15:8])
+ 8'b00000000:
+ begin
+ op_o <= `OP_NOP;
+ end
+ 8'b00000001:
+ begin
+ op_o <= `OP_LDI_L;
+ operand_o <= operand_i;
+ end
+ 8'b00000010:
+ begin
+ op_o <= `OP_MOV;
+ end
+ 8'b00000011:
+ begin
+ op_o <= `OP_JSRA;
+ end
+ 8'b00000100:
+ begin
+ op_o <= `OP_RET;
+ end
+ 8'b00000101:
+ begin
+ op_o <= `OP_ADD_L;
+ end
+ 8'b00000110:
+ begin
+ op_o <= `OP_PUSH;
+ end
+ 8'b00000111:
+ begin
+ op_o <= `OP_POP;
+ end
+ 8'b00001000:
+ begin
+ op_o <= `OP_LDA_L;
+ operand_o <= operand_i;
+ end
+ 8'b00001001:
+ begin
+ op_o <= `OP_STA_L;
+ operand_o <= operand_i;
+ end
+ 8'b00001010:
+ begin
+ op_o <= `OP_LD_L;
+ end
+ 8'b00001011:
+ begin
+ op_o <= `OP_ST_L;
+ end
+ 8'b00001100:
+ begin
+ op_o <= `OP_LDO_L;
+ end
+ 8'b00001101:
+ begin
+ op_o <= `OP_STO_L;
+ end
+ 8'b00001110:
+ begin
+ op_o <= `OP_CMP;
+ end
+ 8'b00001111:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010000:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010001:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010010:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010011:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010100:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010101:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010110:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00010111:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00011000:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00011001:
+ begin
+ op_o <= `OP_JSR;
+ end
+ 8'b00011010:
+ begin
+ op_o <= `OP_JMPA;
+ operand_o <= operand_i;
+ end
+ 8'b00011011:
+ begin
+ op_o <= `OP_LDI_B;
+ end
+ 8'b00011100:
+ begin
+ op_o <= `OP_LD_B;
+ end
+ 8'b00011101:
+ begin
+ op_o <= `OP_LDA_B;
+ end
+ 8'b00011110:
+ begin
+ op_o <= `OP_ST_B;
+ end
+ 8'b00011111:
+ begin
+ op_o <= `OP_STA_B;
+ end
+ 8'b00100000:
+ begin
+ op_o <= `OP_LDI_S;
+ end
+ 8'b00100001:
+ begin
+ op_o <= `OP_LD_S;
+ end
+ 8'b00100010:
+ begin
+ op_o <= `OP_LDA_S;
+ end
+ 8'b00100011:
+ begin
+ op_o <= `OP_ST_S;
+ end
+ 8'b00100100:
+ begin
+ op_o <= `OP_STA_S;
+ end
+ 8'b00100101:
+ begin
+ op_o <= `OP_JMP;
+ end
+ 8'b00100110:
+ begin
+ op_o <= `OP_AND;
+ end
+ 8'b00100111:
+ begin
+ op_o <= `OP_LSHR;
+ end
+ 8'b00101000:
+ begin
+ op_o <= `OP_ASHL;
+ end
+ 8'b00101001:
+ begin
+ op_o <= `OP_SUB_L;
+ end
+ 8'b00101010:
+ begin
+ op_o <= `OP_NEG;
+ end
+ 8'b00101011:
+ begin
+ op_o <= `OP_OR;
+ end
+ 8'b00101100:
+ begin
+ op_o <= `OP_NOT;
+ end
+ 8'b00101101:
+ begin
+ op_o <= `OP_ASHR;
+ end
+ 8'b00101110:
+ begin
+ op_o <= `OP_XOR;
+ end
+ 8'b00101111:
+ begin
+ op_o <= `OP_MUL_L;
+ end
+ 8'b00110000:
+ begin
+ op_o <= `OP_SWI;
+ end
+ 8'b00110001:
+ begin
+ op_o <= `OP_DIV_L;
+ end
+ 8'b00110010:
+ begin
+ op_o <= `OP_UDIV_L;
+ end
+ 8'b00110011:
+ begin
+ op_o <= `OP_MOD_L;
+ end
+ 8'b00110100:
+ begin
+ op_o <= `OP_UMOD_L;
+ end
+ 8'b00110101:
+ begin
+ op_o <= `OP_BRK;
+ end
+ 8'b00110110:
+ begin
+ op_o <= `OP_LDO_B;
+ end
+ 8'b00110111:
+ begin
+ op_o <= `OP_STO_B;
+ end
+ 8'b00111000:
+ begin
+ op_o <= `OP_LDO_S;
+ end
+ 8'b00111001:
+ begin
+ op_o <= `OP_STO_S;
+ end
+ 8'b00111010:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00111011:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00111100:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00111101:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00111110:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b00111111:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b1000????:
+ begin
+ op_o <= `OP_INC;
+ operand_o <= opcode_i[3:0];
+ end
+ 8'b1001????:
+ begin
+ op_o <= `OP_DEC;
+ operand_o <= opcode_i[3:0];
+ end
+ 8'b1010????:
+ begin
+ op_o <= `OP_GSR;
+ end
+ 8'b1011????:
+ begin
+ op_o <= `OP_SSR;
+ end
+ 8'b110000??:
+ begin
+ op_o <= `OP_BEQ;
+ end
+ 8'b110001??:
+ begin
+ op_o <= `OP_BNE;
+ end
+ 8'b110010??:
+ begin
+ op_o <= `OP_BLT;
+ end
+ 8'b110011??:
+ begin
+ op_o <= `OP_BGT;
+ end
+ 8'b110100??:
+ begin
+ op_o <= `OP_BLTU;
+ end
+ 8'b110101??:
+ begin
+ op_o <= `OP_BGTU;
+ end
+ 8'b110110??:
+ begin
+ op_o <= `OP_BGE;
+ end
+ 8'b110111??:
+ begin
+ op_o <= `OP_BLE;
+ end
+ 8'b111000??:
+ begin
+ op_o <= `OP_BGEU;
+ end
+ 8'b111001??:
+ begin
+ op_o <= `OP_BLEU;
+ end
+ 8'b111010??:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b111011??:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b111100??:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b111101??:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b111110??:
+ begin
+ op_o <= `OP_BAD;
+ end
+ 8'b111111??:
+ begin
+ op_o <= `OP_BAD;
+ end
+ endcase // casex (opcode_i)
+ // register_write_enable_o <= (!op_nop) & (op_ldi|op_dec|op_xor|op_sub);
+ end
+ end // always @ (posedge clk_i)
+ end
endmodule // cpu_decode;
View
166 moxie/cores/moxie/cpu_execute.v
@@ -20,15 +20,15 @@
`include "defines.v"
module cpu_execute (/*AUTOARG*/
- // Outputs
- register_write_index_o, register_write_enable_o,
- memory_read_enable_o, memory_write_enable_o, memory_address_o,
- reg_result_o, mem_result_o, riA_o, riB_o, stall_o, branch_flag_o,
- branch_target_o,
- // Inputs
- rst_i, clk_i, stall_i, riA_i, riB_i, regA_i, regB_i,
- register_write_index_i, operand_i, op_i, sp_i, fp_i, PC_i
- );
+ // Outputs
+ register_write_index_o, pipeline_control_bits_o, memory_address_o,
+ reg_result_o, mem_result_o, riA_o, riB_o, stall_o, branch_flag_o,
+ branch_target_o,
+ // Inputs
+ rst_i, clk_i, stall_i, riA_i, riB_i, regA_i, regB_i,
+ pipeline_control_bits_i, register_write_index_i, operand_i, op_i,
+ sp_i, fp_i, PC_i
+ );
parameter [1:0] STATE_READY = 2'b00,
STATE_JSR1 = 2'b01,
@@ -45,6 +45,7 @@ module cpu_execute (/*AUTOARG*/
input [3:0] riB_i;
input [31:0] regA_i;
input [31:0] regB_i;
+ input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
input [3:0] register_write_index_i;
input [31:0] operand_i;
input [5:0] op_i;
@@ -54,9 +55,7 @@ module cpu_execute (/*AUTOARG*/
// --- Outputs --------------------------------------------------
output [3:0] register_write_index_o;
- output [0:0] register_write_enable_o;
- output [0:0] memory_read_enable_o;
- output [0:0] memory_write_enable_o;
+ output [`PCB_WIDTH-1:0] pipeline_control_bits_o;
output [31:0] memory_address_o;
output [31:0] reg_result_o;
output [31:0] mem_result_o;
@@ -73,9 +72,7 @@ module cpu_execute (/*AUTOARG*/
reg [31:0] branch_target_o;
reg [3:0] register_write_index_o;
- reg [0:0] register_write_enable_o;
- reg [0:0] memory_read_enable_o;
- reg [0:0] memory_write_enable_o;
+ reg [`PCB_WIDTH-1:0] pipeline_control_bits_o;
reg [31:0] memory_address_o;
reg [31:0] reg_result_o;
reg [31:0] mem_result_o;
@@ -96,19 +93,16 @@ module cpu_execute (/*AUTOARG*/
always @(posedge rst_i or posedge clk_i)
if (rst_i) begin
- register_write_enable_o <= 0;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
+ pipeline_control_bits_o <= 5'b00000;
stall_o <= 0;
end else
if (stall_i)
begin
$display ("EXECUTE STALL");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 0;
+ pipeline_control_bits_o <= 5'b00000;
end
else begin
+ pipeline_control_bits_o <= pipeline_control_bits_i;
case (current_state)
STATE_READY:
begin
@@ -116,9 +110,6 @@ module cpu_execute (/*AUTOARG*/
`OP_ADD_L:
begin
reg_result_o <= regA_i + regB_i;
- register_write_enable_o <= 1;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -126,9 +117,6 @@ module cpu_execute (/*AUTOARG*/
`OP_AND:
begin
reg_result_o <= regA_i & regB_i;
- register_write_enable_o <= 1;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -136,120 +124,90 @@ module cpu_execute (/*AUTOARG*/
`OP_ASHL:
begin
$display ("Executing OP_ASHL");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_ASHR:
begin
$display ("Executing OP_ASHR");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BAD:
begin
$display ("Executing OP_BAD");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BEQ:
begin
$display ("Executing OP_BEQ");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BGE:
begin
$display ("Executing OP_BGE");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BGEU:
begin
$display ("Executing OP_BGEU");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BGT:
begin
$display ("Executing OP_BGT");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BGTU:
begin
$display ("Executing OP_BGTU");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BLE:
begin
$display ("Executing OP_BLE");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BLEU:
begin
$display ("Executing OP_BLEU");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BLT:
begin
$display ("Executing OP_BLT");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BLTU:
begin
$display ("Executing OP_BLTU");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BNE:
begin
$display ("Executing OP_BNE");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_BRK:
begin
$display ("Executing OP_BRK");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_CMP:
begin
$display ("Executing OP_CMP");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -257,9 +215,6 @@ module cpu_execute (/*AUTOARG*/
begin
$display ("EXECUTE OP_DEC: 0x%x", operand_i);
reg_result_o <= regA_i - operand_i;
- register_write_enable_o <= 1;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -267,16 +222,12 @@ module cpu_execute (/*AUTOARG*/
`OP_DIV_L:
begin
$display ("Executing OP_DIV_L");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_GSR:
begin
$display ("Executing OP_GSR");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -284,9 +235,6 @@ module cpu_execute (/*AUTOARG*/
begin
$display ("EXECUTE OP_INC: 0x%x", operand_i);
reg_result_o <= regA_i + operand_i;
- register_write_enable_o <= 1;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -294,18 +242,12 @@ module cpu_execute (/*AUTOARG*/
`OP_JMP:
begin
branch_target_o <= regA_i;
- register_write_enable_o <= 0;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_JMPA:
begin
branch_target_o <= operand_i;
- register_write_enable_o <= 0;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -315,9 +257,6 @@ module cpu_execute (/*AUTOARG*/
reg_result_o <= sp_i - 8;
memory_address_o <= sp_i - 8;
mem_result_o <= PC_i+6;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 1;
- register_write_enable_o <= 1;
register_write_index_o <= 1; // $sp
next_state <= STATE_JSR1;
stall_o <= 1;
@@ -325,48 +264,36 @@ module cpu_execute (/*AUTOARG*/
`OP_JSRA:
begin
$display ("Executing OP_JSRA");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_JSR1;
stall_o <= 1;
end
`OP_LDA_B:
begin
$display ("Executing OP_LDA_B");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LDA_L:
begin
memory_address_o <= operand_i;
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LDA_S:
begin
$display ("Executing OP_LDA_S");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LD_B:
begin
$display ("Executing OP_LD_B");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LDI_B:
begin
$display ("Executing OP_LDI_B");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -374,9 +301,6 @@ module cpu_execute (/*AUTOARG*/
begin
$display ("EXECUTE OP_LDI_L: 0x%x", operand_i);
reg_result_o <= operand_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -384,73 +308,55 @@ module cpu_execute (/*AUTOARG*/
`OP_LDI_S:
begin
$display ("Executing OP_LDI_S");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LD_L:
begin
$display ("Executing OP_LD_L");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LDO_B:
begin
$display ("Executing OP_LDO_B");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LDO_L:
begin
$display ("Executing OP_LDO_L");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LDO_S:
begin
$display ("Executing OP_LDO_S");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LD_S:
begin
$display ("Executing OP_LD_S");
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_LSHR:
begin
$display ("Executing OP_LSHR");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_MOD_L:
begin
$display ("Executing OP_MOD_L");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_MOV:
begin
+ $display ("Executing OP_MOV");
reg_result_o <= regB_i;
- memory_write_enable_o <= 0;
- memory_read_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -458,41 +364,29 @@ module cpu_execute (/*AUTOARG*/
`OP_MUL_L:
begin
$display ("Executing OP_MUL_L");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_NEG:
begin
$display ("Executing OP_NEG");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_NOP:
begin
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_NOT:
begin
$display ("Executing OP_NOT");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_OR:
begin
reg_result_o <= regA_i | regB_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -502,9 +396,6 @@ module cpu_execute (/*AUTOARG*/
// Decrement pointer register by 4 bytes.
memory_address_o <= regA_i;
mem_result_o <= regA_i - 4;
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -515,9 +406,6 @@ module cpu_execute (/*AUTOARG*/
reg_result_o <= regA_i - 4;
memory_address_o <= regA_i - 4;
mem_result_o <= regB_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 1;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -527,9 +415,6 @@ module cpu_execute (/*AUTOARG*/
// Increment $sp by 8
memory_address_o <= sp_i;
reg_result_o <= sp_i + 8;
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= 1; // $sp
next_state <= STATE_RET1;
stall_o <= 0;
@@ -537,8 +422,6 @@ module cpu_execute (/*AUTOARG*/
`OP_SSR:
begin
$display ("Executing OP_SSR");
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -546,16 +429,12 @@ module cpu_execute (/*AUTOARG*/
begin
$display ("Executing OP_STA_B");
mem_result_o <= regA_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 1;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_STA_L:
begin
mem_result_o <= regA_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 1;
memory_address_o <= operand_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -605,9 +484,6 @@ module cpu_execute (/*AUTOARG*/
`OP_SUB_L:
begin
reg_result_o <= regA_i - regB_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -633,9 +509,6 @@ module cpu_execute (/*AUTOARG*/
`OP_XOR:
begin
reg_result_o <= regA_i ^ regB_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
register_write_index_o <= register_write_index_i;
stall_o <= 0;
end
@@ -647,9 +520,6 @@ module cpu_execute (/*AUTOARG*/
reg_result_o <= sp_i - 4;
memory_address_o <= sp_i - 4;
mem_result_o <= fp_i;
- memory_read_enable_o <= 0;
- memory_write_enable_o <= 1;
- register_write_enable_o <= 1;
register_write_index_o <= 1; // $sp
branch_target_o <= operand_i;
next_state <= STATE_READY;
@@ -660,9 +530,7 @@ module cpu_execute (/*AUTOARG*/
// Increment $sp by 4 bytes.
reg_result_o <= sp_i + 4;
memory_address_o <= sp_i + 4;
- memory_read_enable_o <= 1;
- memory_write_enable_o <= 0;
- register_write_enable_o <= 1;
+ pipeline_control_bits_o <= 5'b10000;
// This is all wrong
register_write_index_o <= 1; // $sp
branch_target_o <= operand_i;
View
25 moxie/cores/moxie/cpu_write.v
@@ -18,24 +18,23 @@
// 02110-1301, USA.
module cpu_write (/*AUTOARG*/
- // Outputs
- register_write_index_o, register_we_o, reg_result_o,
- // Inputs
- rst_i, clk_i, register_write_index_i, register_we_i, memory_we_i,
- loadp_i, memory_address_i, reg_result_i, mem_result_i
- );
+ // Outputs
+ register_write_index_o, register_we_o, reg_result_o,
+ // Inputs
+ rst_i, clk_i, pipeline_control_bits_i, register_write_index_i,
+ memory_address_i, reg_result_i, mem_result_i
+ );
// --- Clock and Reset ------------------------------------------
input rst_i, clk_i;
+ input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
input [3:0] register_write_index_i;
- input [0:0] register_we_i;
- input [0:0] memory_we_i;
- input [0:0] loadp_i;
input [31:0] memory_address_i;
input [31:0] reg_result_i;
input [31:0] mem_result_i;
+
output [3:0] register_write_index_o;
output [0:0] register_we_o;
output [31:0] reg_result_o;
@@ -43,16 +42,16 @@ module cpu_write (/*AUTOARG*/
wire [31:0] data;
wire [3:0] register_write_index_o = register_write_index_i;
- wire [0:0] register_we_o = register_we_i;
+ wire [0:0] register_we_o = pipeline_control_bits_i[`PCB_WR];
- // loadp_i is high if we are loading memory from cache
- wire [31:0] reg_result_o = loadp_i ? data : reg_result_i;
+ // PCB_RM is high if we are loading memory from cache
+ wire [31:0] reg_result_o = pipeline_control_bits_i[`PCB_RM] ? data : reg_result_i;
// The data cache. Fake. Never stalls. Note that we can do a single
// cycle memory-to-memory transfer.
dcache cache (.clk_i (clk_i),
.rst_i (rst_i),
- .we_i (memory_we_i),
+ .we_i (pipeline_control_bits_i[`PCB_WM]),
.address_i (memory_address_i),
.data_i (mem_result_i),
.data_o (data));
View
7 moxie/cores/moxie/defines.v
@@ -17,6 +17,13 @@
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
// 02110-1301, USA.
+`define PCB_WIDTH 5
+`define PCB_WR 4
+`define PCB_RA 3
+`define PCB_RB 2
+`define PCB_WM 1
+`define PCB_RM 0
+
`define OP_ADD_L 6'b000000
`define OP_AND 6'b000001
`define OP_ASHL 6'b000010
View
112 moxie/cores/moxie/microcode.org
@@ -3,62 +3,64 @@ Form 1 Instruction Microcode
name - instruction name
code - form 1 opcode value
-w reg? - writes to register A?
-r A? - reads register A?
-r B? - reads register B?
+wr? - writes to register A?
+rA? - reads register A?
+rB? - reads register B?
+wm? - writes to memory?
+rm? - reads from memory?
notes - misc. comments
-|--------+----------+--------+------+------+-------|
-| name | code | w reg? | r A? | r B? | notes |
-|--------+----------+--------+------+------+-------|
-| nop | 00000000 | 0 | 0 | 0 | |
-| ldi.l | 00000001 | 1 | 0 | 0 | |
-| mov | 00000010 | 1 | 0 | 1 | |
-| jsra | 00000011 | 0 | 0 | 0 | |
-| ret | 00000100 | 0 | 0 | 0 | |
-| add.l | 00000101 | 1 | 1 | 1 | |
-| push | 00000110 | 0 | 0 | 0 | |
-| pop | 00000111 | 0 | 0 | 0 | |
-| lda.l | 00001000 | 1 | 0 | 0 | |
-| sta.l | 00001001 | 0 | 1 | 0 | |
-| ld.l | 00001010 | 1 | 1 | 0 | |
-| st.l | 00001011 | 0 | 1 | 0 | |
-| ldo.l | 00001100 | 1 | 1 | 1 | |
-| sto.l | 00001101 | 0 | 1 | 1 | |
-| cmp | 00001110 | 0 | 1 | 1 | |
-| jsr | 00011001 | 0 | 1 | 0 | |
-| jmpa | 00011010 | 0 | 0 | 0 | |
-| ldi.b | 00011011 | 1 | 0 | 0 | |
-| ld.b | 00011100 | 1 | 1 | 0 | |
-| lda.b | 00011101 | 1 | 0 | 0 | |
-| st.b | 00011110 | 0 | 1 | 1 | |
-| sta.b | 00011111 | 0 | 1 | 0 | |
-| ldi.s | 00100000 | 1 | 0 | 0 | |
-| ld.s | 00100001 | 1 | 1 | 0 | |
-| lda.s | 00100010 | 1 | 1 | 0 | |
-| st.s | 00100011 | 0 | 1 | 1 | |
-| sta.s | 00100100 | 0 | 1 | 0 | |
-| jmp | 00100101 | 0 | 0 | 0 | |
-| and | 00100110 | 1 | 1 | 1 | |
-| lshr | 00100111 | 1 | 1 | 1 | |
-| ashr | 00101000 | 1 | 1 | 1 | |
-| sub.l | 00101001 | 1 | 1 | 1 | |
-| neg | 00101010 | 1 | 1 | 1 | |
-| or | 00101011 | 1 | 1 | 1 | |
-| not | 00101100 | 1 | 1 | 1 | |
-| ashr | 00101101 | 1 | 1 | 1 | |
-| xor | 00101110 | 1 | 1 | 1 | |
-| mul.l | 00101111 | 1 | 1 | 1 | |
-| swi | 00110000 | 0 | 0 | 0 | |
-| div.l | 00110001 | 1 | 1 | 1 | |
-| udiv.l | 00110010 | 1 | 1 | 1 | |
-| mod.l | 00110011 | 1 | 1 | 1 | |
-| umod.l | 00110100 | 1 | 1 | 1 | |
-| brk | 00110101 | 0 | 0 | 0 | |
-| ldo.b | 00110110 | 1 | 1 | 1 | |
-| sto.b | 00110111 | 0 | 1 | 1 | |
-| ldo.s | 00111000 | 1 | 1 | 1 | |
-| sto.s | 00111001 | 0 | 0 | 0 | |
-|--------+----------+--------+------+------+-------|
+|--------+----------+-----+-----+-----+-----+-----+-------|
+| name | code | wr? | rA? | rB? | wm? | rm? | notes |
+|--------+----------+-----+-----+-----+-----+-----+-------|
+| nop | 00000000 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.l | 00000001 | 1 | 0 | 0 | 0 | 0 | |
+| mov | 00000010 | 1 | 0 | 1 | 0 | 0 | |
+| jsra | 00000011 | 0 | 0 | 0 | 0 | 0 | |
+| ret | 00000100 | 0 | 0 | 0 | 0 | 0 | |
+| add.l | 00000101 | 1 | 1 | 1 | 0 | 0 | |
+| push | 00000110 | 0 | 0 | 0 | 0 | 0 | |
+| pop | 00000111 | 0 | 0 | 0 | 0 | 0 | |
+| lda.l | 00001000 | 1 | 0 | 0 | 0 | 1 | |
+| sta.l | 00001001 | 0 | 1 | 0 | 1 | 0 | |
+| ld.l | 00001010 | 1 | 1 | 0 | 0 | 1 | |
+| st.l | 00001011 | 0 | 1 | 0 | 1 | 0 | |
+| ldo.l | 00001100 | 1 | 1 | 1 | 0 | 1 | |
+| sto.l | 00001101 | 0 | 1 | 1 | 1 | 0 | |
+| cmp | 00001110 | 0 | 1 | 1 | 0 | 0 | |
+| jsr | 00011001 | 0 | 1 | 0 | 0 | 0 | |
+| jmpa | 00011010 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.b | 00011011 | 1 | 0 | 0 | 0 | 0 | |
+| ld.b | 00011100 | 1 | 1 | 0 | 0 | 1 | |
+| lda.b | 00011101 | 1 | 0 | 0 | 0 | 1 | |
+| st.b | 00011110 | 0 | 1 | 1 | 1 | 0 | |
+| sta.b | 00011111 | 0 | 1 | 0 | 1 | 0 | |
+| ldi.s | 00100000 | 1 | 0 | 0 | 0 | 0 | |
+| ld.s | 00100001 | 1 | 1 | 0 | 0 | 1 | |
+| lda.s | 00100010 | 1 | 1 | 0 | 0 | 1 | |
+| st.s | 00100011 | 0 | 1 | 1 | 1 | 0 | |
+| sta.s | 00100100 | 0 | 1 | 0 | 1 | 0 | |
+| jmp | 00100101 | 0 | 0 | 0 | 0 | 0 | |
+| and | 00100110 | 1 | 1 | 1 | 0 | 0 | |
+| lshr | 00100111 | 1 | 1 | 1 | 0 | 0 | |
+| ashr | 00101000 | 1 | 1 | 1 | 0 | 0 | |
+| sub.l | 00101001 | 1 | 1 | 1 | 0 | 0 | |
+| neg | 00101010 | 1 | 1 | 1 | 0 | 0 | |
+| or | 00101011 | 1 | 1 | 1 | 0 | 0 | |
+| not | 00101100 | 1 | 1 | 1 | 0 | 0 | |
+| ashr | 00101101 | 1 | 1 | 1 | 0 | 0 | |
+| xor | 00101110 | 1 | 1 | 1 | 0 | 0 | |
+| mul.l | 00101111 | 1 | 1 | 1 | 0 | 0 | |
+| swi | 00110000 | 0 | 0 | 0 | 0 | 0 | |
+| div.l | 00110001 | 1 | 1 | 1 | 0 | 0 | |
+| udiv.l | 00110010 | 1 | 1 | 1 | 0 | 0 | |
+| mod.l | 00110011 | 1 | 1 | 1 | 0 | 0 | |
+| umod.l | 00110100 | 1 | 1 | 1 | 0 | 0 | |
+| brk | 00110101 | 0 | 0 | 0 | 0 | 0 | |
+| ldo.b | 00110110 | 1 | 1 | 1 | 0 | 1 | |
+| sto.b | 00110111 | 0 | 1 | 1 | 1 | 0 | |
+| ldo.s | 00111000 | 1 | 1 | 1 | 0 | 1 | |
+| sto.s | 00111001 | 0 | 0 | 0 | 1 | 0 | |
+|--------+----------+-----+-----+-----+-----+-----+-------|
View
8 moxie/cores/moxie/microcode.v
@@ -27,16 +27,16 @@ module microcode (/*AUTOARG*/
);
input [7:0] opcode;
- output [2:0] q;
+ output [`PCB_WIDTH-1:0] q;
- reg [2:0] rom[0:63];
+ reg [`PCB_WIDTH-1:0] rom[0:63];
initial $readmemb("microcode.bin", rom);
- wire [2:0] f1, f2;
+ wire [`PCB_WIDTH-1:0] f1, f2;
assign f1 = rom[opcode[5:0]];
- assign f2 = 3'b111;
+ assign f2 = 5'b11111;
assign q = (opcode[7] ? f2 : f1);
View
50 moxie/cores/moxie/moxie.v
@@ -64,11 +64,9 @@ module moxie (/*AUTOARG*/
wire [0:0] fd_valid;
wire [31:0] dx_operand;
wire [31:0] dx_PC;
- wire [0:0] dx_register_write_enable;
+ wire [`PCB_WIDTH-1:0] dx_pipeline_control_bits;
wire [5:0] dx_op;
- wire [0:0] xw_register_write_enable;
- wire [0:0] xw_loadp;
- wire [0:0] xw_memory_we;
+ wire [`PCB_WIDTH-1:0] xw_pipeline_control_bits;
wire [0:0] wr_register_write_enable;
wire [3:0] dx_register_write_index;
wire [3:0] xw_register_write_index;
@@ -90,10 +88,8 @@ module moxie (/*AUTOARG*/
wire [31:0] rx_reg_value1;
wire [31:0] rx_reg_value2;
- wire [3:0] dx_reg_index1;
- wire [3:0] dx_reg_index2;
- wire [3:0] xr_reg_index1;
- wire [3:0] xr_reg_index2;
+ wire [3:0] dr_reg_index1;
+ wire [3:0] dr_reg_index2;
wire [0:0] stall_x;
@@ -125,8 +121,8 @@ module moxie (/*AUTOARG*/
.write_enable0_i (wr_register_write_enable),
.write_enable1_i (0),
.reg_write_index0_i (wr_register_write_index),
- .reg_read_index0_i (xr_reg_index1),
- .reg_read_index1_i (xr_reg_index2),
+ .reg_read_index0_i (dr_reg_index1),
+ .reg_read_index1_i (dr_reg_index2),
.sp_o (rx_sp),
.fp_o (rx_fp),
.value0_i (wr_reg_result),
@@ -167,12 +163,12 @@ module moxie (/*AUTOARG*/
.valid_i (fd_valid),
.stall_i (hazard_war | stall_x),
// Outputs
- .register_write_enable_o (dx_register_write_enable),
+ .pipeline_control_bits_o (dx_pipeline_control_bits),
.register_write_index_o (dx_register_write_index),
.operand_o (dx_operand),
.PC_o (dx_PC),
- .riA_o (dx_reg_index1),
- .riB_o (dx_reg_index2),
+ .riA_o (dr_reg_index1),
+ .riB_o (dr_reg_index2),
.op_o (dx_op));
cpu_execute stage_execute (// Inputs
@@ -183,23 +179,18 @@ module moxie (/*AUTOARG*/
.op_i (dx_op),
.PC_i (dx_PC),
.operand_i (dx_operand[31:0]),
- .riA_i (dx_reg_index1),
- .riB_i (dx_reg_index2),
- .riA_o (xr_reg_index1),
- .riB_o (xr_reg_index2),
.regA_i (rx_reg_value1),
.regB_i (rx_reg_value2),
.branch_flag_o (xf_branch_flag),
.branch_target_o (xf_branch_target),
+ .pipeline_control_bits_i (dx_pipeline_control_bits),
.register_write_index_i (dx_register_write_index),
// Outputs
- .register_write_enable_o (xw_register_write_enable),
+ .pipeline_control_bits_o (xw_pipeline_control_bits),
.register_write_index_o (xw_register_write_index),
.reg_result_o (xw_reg_result),
.mem_result_o (xw_mem_result),
.memory_address_o (xw_memory_address),
- .memory_read_enable_o (xw_loadp),
- .memory_write_enable_o (xw_memory_we),
.sp_i (rx_sp),
.fp_i (rx_fp));
@@ -207,9 +198,7 @@ module moxie (/*AUTOARG*/
.rst_i (rst_i),
.clk_i (clk_i),
.register_write_index_i (xw_register_write_index),
- .register_we_i (xw_register_write_enable),
- .loadp_i (xw_loadp),
- .memory_we_i (xw_memory_we),
+ .pipeline_control_bits_i (xw_pipeline_control_bits),
.memory_address_i (xw_memory_address),
.reg_result_i (xw_reg_result),
.mem_result_i (xw_mem_result),
@@ -218,8 +207,15 @@ module moxie (/*AUTOARG*/
.register_we_o (wr_register_write_enable),
.reg_result_o (wr_reg_result));
- assign hazard_war = xw_register_write_enable
- & ((xw_register_write_index == dx_reg_index1)
- | (xw_register_write_index == dx_reg_index2));
-
+ assign hazard_war = 0;
+
+
+ // assign hazard_war = dx_pipeline_control_bits[`PCB_RB] &
+ // xw_pipeline_control_bits[`PCB_WR] &
+ // xw_register_write_index == dx_reg_index2;
+
+ // assign hazard_war = (xw_pipeline_control_bits[`PCB_WR]
+ // & ((xw_register_write_index == dx_reg_index1)
+ // | (xw_register_write_index == dx_reg_index2)));
+
endmodule // moxie
View
10 scripts/microcoder.lisp
@@ -36,7 +36,7 @@
(loop for filepos = (file-position in)
for line = (read-line in nil)
until (let ((s (cl-ppcre:split "\\|" line)))
- (equal (length s) 7)))
+ (equal (length s) 9)))
(read-line in nil)
;; We're at the table contents now. Parse it and write our new
@@ -48,11 +48,11 @@
for line = (read-line in nil)
while line do
(let ((s (cl-ppcre:split "\\|" line)))
- (if (equal 7 (length s))
- (destructuring-bind (junk1 name code wreg? rA? rb? &rest junk2)
+ (if (equal 9 (length s))
+ (destructuring-bind (junk1 name code wr? rA? rB? rm? wm? &rest junk2)
(mapcar (lambda (v) (string-trim " " v)) s)
(setf (aref opcode-array (parse-integer code :radix 2))
- (list name wreg? rA? rb?))))))
+ (list name wr? rA? rB? rm? wm?))))))
(loop for i from 0 to 63
do (let ((o (aref opcode-array i)))
(if o
@@ -63,7 +63,7 @@
((equal n 1) (format out "1"))
(t (error "bad table entry")))))
(cdr o))
- (format out "000"))
+ (format out "00000"))
(format out "~%"))))
(close in)))
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