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Implement push instruction

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1 parent 5d72550 commit 607c5ffd70fd74312d1378ae400f98cd85034cdf @atgreen committed Oct 11, 2011
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43 moxie/cores/moxie/cpu_execute.v
@@ -23,7 +23,8 @@ module cpu_execute (/*AUTOARG*/
// Outputs
register_write_index_o, register_write_enable_o,
memory_read_enable_o, memory_write_enable_o, memory_address_o,
- result_o, riA_o, riB_o, branch_flag_o, branch_target_o,
+ reg_result_o, mem_result_o, riA_o, riB_o, branch_flag_o,
+ branch_target_o,
// Inputs
rst_i, clk_i, stall_i, riA_i, riB_i, regA_i, regB_i,
register_write_index_i, operand_i, op_i
@@ -49,7 +50,9 @@ module cpu_execute (/*AUTOARG*/
output [0:0] register_write_enable_o;
output [0:0] memory_read_enable_o;
output [0:0] memory_write_enable_o;
- output [31:0] memory_address_o; output [31:0] result_o;
+ output [31:0] memory_address_o;
+ output [31:0] reg_result_o;
+ output [31:0] mem_result_o;
output [3:0] riA_o;
output [3:0] riB_o;
@@ -64,10 +67,11 @@ module cpu_execute (/*AUTOARG*/
reg [0:0] memory_read_enable_o;
reg [0:0] memory_write_enable_o;
reg [31:0] memory_address_o;
- reg [31:0] result_o;
+ reg [31:0] reg_result_o;
+ reg [31:0] mem_result_o;
assign riA_o = riA_i;
- assign riB_o = riB_o;
+ assign riB_o = riB_i;
always @(posedge rst_i or posedge clk_i)
if (rst_i == 1)
@@ -91,15 +95,15 @@ module cpu_execute (/*AUTOARG*/
case (op_i)
`OP_ADD_L:
begin
- result_o <= regA_i + regB_i;
+ reg_result_o <= regA_i + regB_i;
register_write_enable_o <= 1;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
register_write_index_o <= register_write_index_i;
end
`OP_AND:
begin
- result_o <= regA_i & regB_i;
+ reg_result_o <= regA_i & regB_i;
register_write_enable_o <= 1;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
@@ -198,7 +202,7 @@ module cpu_execute (/*AUTOARG*/
`OP_DEC:
begin
$display ("EXECUTE OP_DEC: 0x%x", operand_i);
- result_o <= regA_i - operand_i;
+ reg_result_o <= regA_i - operand_i;
register_write_enable_o <= 1;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
@@ -219,7 +223,7 @@ module cpu_execute (/*AUTOARG*/
`OP_INC:
begin
$display ("EXECUTE OP_INC: 0x%x", operand_i);
- result_o <= regA_i + operand_i;
+ reg_result_o <= regA_i + operand_i;
register_write_enable_o <= 1;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
@@ -284,7 +288,7 @@ module cpu_execute (/*AUTOARG*/
`OP_LDI_L:
begin
$display ("EXECUTE OP_LDI_L: 0x%x", operand_i);
- result_o <= operand_i;
+ reg_result_o <= operand_i;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
register_write_enable_o <= 1;
@@ -340,7 +344,7 @@ module cpu_execute (/*AUTOARG*/
end
`OP_MOV:
begin
- result_o <= regB_i;
+ reg_result_o <= regB_i;
memory_write_enable_o <= 0;
memory_read_enable_o <= 0;
register_write_enable_o <= 1;
@@ -372,7 +376,7 @@ module cpu_execute (/*AUTOARG*/
end
`OP_OR:
begin
- result_o <= regA_i | regB_i;
+ reg_result_o <= regA_i | regB_i;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
register_write_enable_o <= 1;
@@ -386,9 +390,14 @@ module cpu_execute (/*AUTOARG*/
end
`OP_PUSH:
begin
- $display ("Executing OP_PUSH");
+ // Decrement pointer register by 4 bytes.
+ reg_result_o <= regA_i - 4;
+ memory_address_o <= regA_i - 4;
+ mem_result_o <= regB_i;
memory_read_enable_o <= 0;
- memory_write_enable_o <= 0;
+ memory_write_enable_o <= 1;
+ register_write_enable_o <= 1;
+ register_write_index_o <= register_write_index_i;
end
`OP_RET:
begin
@@ -405,13 +414,13 @@ module cpu_execute (/*AUTOARG*/
`OP_STA_B:
begin
$display ("Executing OP_STA_B");
- result_o <= regA_i;
+ mem_result_o <= regA_i;
memory_read_enable_o <= 0;
memory_write_enable_o <= 1;
end
`OP_STA_L:
begin
- result_o <= regA_i;
+ mem_result_o <= regA_i;
memory_read_enable_o <= 0;
memory_write_enable_o <= 1;
memory_address_o <= operand_i;
@@ -446,7 +455,7 @@ module cpu_execute (/*AUTOARG*/
end
`OP_SUB_L:
begin
- result_o <= regA_i - regB_i;
+ reg_result_o <= regA_i - regB_i;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
register_write_enable_o <= 1;
@@ -466,7 +475,7 @@ module cpu_execute (/*AUTOARG*/
end
`OP_XOR:
begin
- result_o <= regA_i ^ regB_i;
+ reg_result_o <= regA_i ^ regB_i;
memory_read_enable_o <= 0;
memory_write_enable_o <= 0;
register_write_enable_o <= 1;
View
13 moxie/cores/moxie/cpu_write.v
@@ -19,10 +19,10 @@
module cpu_write (/*AUTOARG*/
// Outputs
- register_write_index_o, register_we_o, result_o,
+ register_write_index_o, register_we_o, reg_result_o,
// Inputs
rst_i, clk_i, register_write_index_i, register_we_i, memory_we_i,
- loadp_i, memory_address_i, result_i
+ loadp_i, memory_address_i, reg_result_i, mem_result_i
);
// --- Clock and Reset ------------------------------------------
@@ -33,27 +33,28 @@ module cpu_write (/*AUTOARG*/
input [0:0] memory_we_i;
input [0:0] loadp_i;
input [31:0] memory_address_i;
- input [31:0] result_i;
+ input [31:0] reg_result_i;
+ input [31:0] mem_result_i;
output [3:0] register_write_index_o;
output [0:0] register_we_o;
- output [31:0] result_o;
+ output [31:0] reg_result_o;
wire [31:0] data;
wire [3:0] register_write_index_o = register_write_index_i;
wire [0:0] register_we_o = register_we_i;
// loadp_i is high if we are loading memory from cache
- wire [31:0] result_o = loadp_i ? data : result_i;
+ wire [31:0] reg_result_o = loadp_i ? data : reg_result_i;
// The data cache. Fake. Never stalls. Note that we can do a single
// cycle memory-to-memory transfer.
dcache cache (.clk_i (clk_i),
.rst_i (rst_i),
.we_i (memory_we_i),
.address_i (memory_address_i),
- .data_i (result_o),
+ .data_i (mem_result_i),
.data_o (data));
endmodule // cpu_write
View
15 moxie/cores/moxie/moxie.v
@@ -71,9 +71,10 @@ module moxie (/*AUTOARG*/
wire [3:0] dx_register_write_index;
wire [3:0] xw_register_write_index;
wire [31:0] xw_memory_address;
- wire [31:0] xw_result;
+ wire [31:0] xw_reg_result;
+ wire [31:0] xw_mem_result;
wire [3:0] wr_register_write_index;
- wire [31:0] wr_result;
+ wire [31:0] wr_reg_result;
wire [3:0] dx_regA;
wire [3:0] dx_regB;
wire [3:0] dx_regC;
@@ -116,7 +117,7 @@ module moxie (/*AUTOARG*/
.reg_write_index_i (wr_register_write_index),
.reg_read_index1_i (xr_reg_index1),
.reg_read_index2_i (xr_reg_index2),
- .value_i (wr_result));
+ .value_i (wr_reg_result));
always @(posedge clk_i)
if (rst_i) begin
@@ -176,7 +177,8 @@ module moxie (/*AUTOARG*/
// Outputs
.register_write_enable_o (xw_register_write_enable),
.register_write_index_o (xw_register_write_index),
- .result_o (xw_result),
+ .reg_result_o (xw_reg_result),
+ .mem_result_o (xw_mem_result),
.memory_address_o (xw_memory_address),
.memory_read_enable_o (xw_loadp),
.memory_write_enable_o (xw_memory_we));
@@ -189,11 +191,12 @@ module moxie (/*AUTOARG*/
.loadp_i (xw_loadp),
.memory_we_i (xw_memory_we),
.memory_address_i (xw_memory_address),
- .result_i (xw_result),
+ .reg_result_i (xw_reg_result),
+ .mem_result_i (xw_mem_result),
// Outputs
.register_write_index_o (wr_register_write_index),
.register_we_o (wr_register_write_enable),
- .result_o (wr_result));
+ .reg_result_o (wr_reg_result));
assign hazard_war = 0;
View
3 moxie/firmware/bootrom.s
@@ -5,7 +5,8 @@
mov $r2, $r0
mov $r3, $r0
mov $r4, $r0
-loop: inc $r0, 0x1 # Increment $r0
+loop: push $sp, $r0
+ inc $r0, 0x1 # Increment $r0
inc $r1, 0x1
inc $r2, 0x1
inc $r3, 0x1
View
20 moxie/soc/muskoka/gtkwave/muskoka.sav
@@ -1,4 +1,4 @@
-[timestart] 1427860
+[timestart] 1972780
[size] 1680 993
[pos] -1 -1
*-14.000000 86580 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@@ -70,24 +70,24 @@ sim.soc.core.stage_execute.riA_i[3:0]
sim.soc.core.stage_execute.riB_i[3:0]
@22
sim.soc.core.stage_execute.operand_i[31:0]
-sim.soc.core.stage_execute.result_o[31:0]
@1000200
-EXECUTE UNIT
@800200
-WRITE UNIT
-@22
-sim.soc.core.stage_write.result_i[31:0]
@2022
^2 ../gtkwave/gtkwave-regs.txt
sim.soc.core.stage_write.register_write_index_i[3:0]
-@22
-sim.soc.core.stage_write.cache.address_i[31:0]
@28
-sim.soc.core.stage_write.cache.we_i
+sim.soc.core.stage_write.memory_we_i
@22
-sim.soc.core.stage_write.cache.data_i[31:0]
-@23
-sim.soc.core.stage_write.cache.data_o[31:0]
+sim.soc.core.stage_write.memory_address_i[31:0]
+sim.soc.core.stage_write.mem_result_i[31:0]
+sim.soc.core.stage_write.reg_result_i[31:0]
+@28
+sim.soc.core.stage_write.register_we_i
+@2023
+^2 ../gtkwave/gtkwave-regs.txt
+sim.soc.core.stage_write.register_write_index_i[3:0]
@1000200
-WRITE UNIT
[pattern_trace] 1

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