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Add pipeline forwarding logic and registerfile debug wires

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1 parent 0f5122b commit a641fc0d0b4d011952da0a8560c2adcae00f04e6 @atgreen committed Jun 29, 2012
@@ -12,6 +12,24 @@ module MEM_1w1r(
reg `WORD memory `MEM;
+ // DEBUG WIRES
+ wire [31:0] fp = memory[0];
+ wire [31:0] sp = memory[1];
+ wire [31:0] r0 = memory[2];
+ wire [31:0] r1 = memory[3];
+ wire [31:0] r2 = memory[4];
+ wire [31:0] r3 = memory[5];
+ wire [31:0] r4 = memory[6];
+ wire [31:0] r5 = memory[7];
+ wire [31:0] r6 = memory[8];
+ wire [31:0] r7 = memory[9];
+ wire [31:0] r8 = memory[10];
+ wire [31:0] r9 = memory[11];
+ wire [31:0] r10 = memory[12];
+ wire [31:0] r11 = memory[13];
+ wire [31:0] r12 = memory[14];
+ wire [31:0] r13 = memory[15];
+
always @(negedge clock) begin
if (we)
memory[write_addr] <= write_data;
@@ -25,7 +25,6 @@ module MEM_1w4r(
$dumpvars(1, MEM_1w1r_2);
$dumpvars(1, MEM_1w1r_3);
end
-
MEM_1w1r MEM_1w1r_0(
.clock(clock),
@@ -20,12 +20,12 @@
`include "defines.v"
module cpu_decode (/*AUTOARG*/
- // Outputs
- pipeline_control_bits_o, register_write_index_o, operand_o, riAr_o,
- riBr_o, riA_o, riB_o, op_o, PC_o,
- // Inputs
- rst_i, clk_i, stall_i, opcode_i, operand_i, valid_i, PC_i
- );
+ // Outputs
+ pipeline_control_bits_o, register_write_index_o, operand_o, riA_o,
+ riB_o, op_o, PC_o,
+ // Inputs
+ rst_i, clk_i, stall_i, opcode_i, operand_i, valid_i, PC_i
+ );
// --- Clock and Reset ------------------------------------------
input rst_i, clk_i;
@@ -43,8 +43,6 @@ module cpu_decode (/*AUTOARG*/
output [`PCB_WIDTH-1:0] pipeline_control_bits_o;
output [3:0] register_write_index_o;
output [31:0] operand_o;
- output [3:0] riAr_o;
- output [3:0] riBr_o;
output [3:0] riA_o;
output [3:0] riB_o;
output [5:0] op_o;
@@ -53,8 +51,6 @@ module cpu_decode (/*AUTOARG*/
reg [5:0] op_o;
wire [3:0] riA_o;
wire [3:0] riB_o;
- reg [3:0] riAr_o;
- reg [3:0] riBr_o;
reg [31:0] operand_o;
reg [31:0] PC_o;
reg [`PCB_WIDTH-1:0] pipeline_control_bits_o;
@@ -77,8 +73,6 @@ module cpu_decode (/*AUTOARG*/
always @(posedge clk_i)
begin
if (! stall_i) begin
- riAr_o <= riA_o;
- riBr_o <= riB_o;
PC_o <= PC_i;
end
end
@@ -20,15 +20,15 @@
`include "defines.v"
module cpu_execute (/*AUTOARG*/
- // Outputs
- register_we_o, register_write_index_o, pipeline_control_bits_o,
- memory_address_o, reg_result_o, mem_result_o, riA_o, riB_o,
- stall_o, branch_flag_o, branch_target_o,
- // Inputs
- rst_i, clk_i, stall_i, riA_i, riB_i, regA_i, regB_i,
- pipeline_control_bits_i, register_write_index_i, operand_i, op_i,
- sp_i, fp_i, PC_i
- );
+ // Outputs
+ register_we_o, register_write_index_o, pipeline_control_bits_o,
+ memory_address_o, reg_result_o, mem_result_o, riA_o, riB_o, PC_o,
+ stall_o, branch_flag_o, branch_target_o,
+ // Inputs
+ rst_i, clk_i, stall_i, riA_i, riB_i, regA_i, regB_i,
+ pipeline_control_bits_i, register_write_index_i, operand_i, op_i,
+ sp_i, fp_i, PC_i
+ );
parameter [1:0] STATE_READY = 2'b00,
STATE_JSR1 = 2'b01,
@@ -62,6 +62,7 @@ module cpu_execute (/*AUTOARG*/
output [31:0] mem_result_o;
output [3:0] riA_o;
output [3:0] riB_o;
+ output [31:0] PC_o;
output [0:0] stall_o;
@@ -79,6 +80,8 @@ module cpu_execute (/*AUTOARG*/
reg [31:0] reg_result_o;
reg [31:0] mem_result_o;
+ reg [31:0] PC_o;
+
reg [1:0] current_state, next_state;
assign riA_o = riA_i;
@@ -109,6 +112,7 @@ module cpu_execute (/*AUTOARG*/
end
else begin
pipeline_control_bits_o <= pipeline_control_bits_i;
+ PC_o <= PC_i;
case (current_state)
STATE_READY:
begin
@@ -1,6 +1,6 @@
// cpu_write.v - The writeback unit
//
-// Copyright (c) 2011 Anthony Green. All Rights Reserved.
+// Copyright (c) 2011, 2012 Anthony Green. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it
@@ -18,21 +18,22 @@
// 02110-1301, USA.
module cpu_write (/*AUTOARG*/
- // Outputs
- register_write_index_o, register_we_o, reg_result_o,
- // Inputs
- rst_i, clk_i, pipeline_control_bits_i, register_write_index_i,
- memory_address_i, reg_result_i, mem_result_i
- );
+ // Outputs
+ register_write_index_o, register_we_o, reg_result_o,
+ // Inputs
+ rst_i, clk_i, pipeline_control_bits_i, register_write_index_i,
+ memory_address_i, reg_result_i, mem_result_i, PC_i
+ );
// --- Clock and Reset ------------------------------------------
input rst_i, clk_i;
- input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
+ input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
input [3:0] register_write_index_i;
input [31:0] memory_address_i;
input [31:0] reg_result_i;
input [31:0] mem_result_i;
+ input [31:0] PC_i;
output [3:0] register_write_index_o;
@@ -13,54 +13,54 @@ notes - misc. comments
|--------+----------+-----+-----+-----+-----+-----+-------|
| name | code | wr? | rA? | rB? | wm? | rm? | notes |
|--------+----------+-----+-----+-----+-----+-----+-------|
-| nop | 00000000 | 0 | 0 | 0 | 0 | 0 | |
-| ldi.l | 00000001 | 1 | 0 | 0 | 0 | 0 | |
-| mov | 00000010 | 1 | 0 | 1 | 0 | 0 | |
-| jsra | 00000011 | 0 | 0 | 0 | 0 | 0 | |
-| ret | 00000100 | 0 | 0 | 0 | 0 | 0 | |
-| add.l | 00000101 | 1 | 1 | 1 | 0 | 0 | |
-| push | 00000110 | 0 | 0 | 0 | 0 | 0 | |
-| pop | 00000111 | 0 | 0 | 0 | 0 | 0 | |
-| lda.l | 00001000 | 1 | 0 | 0 | 0 | 1 | |
-| sta.l | 00001001 | 0 | 1 | 0 | 1 | 0 | |
-| ld.l | 00001010 | 1 | 1 | 0 | 0 | 1 | |
-| st.l | 00001011 | 0 | 1 | 0 | 1 | 0 | |
-| ldo.l | 00001100 | 1 | 1 | 1 | 0 | 1 | |
-| sto.l | 00001101 | 0 | 1 | 1 | 1 | 0 | |
-| cmp | 00001110 | 0 | 1 | 1 | 0 | 0 | |
-| jsr | 00011001 | 0 | 1 | 0 | 0 | 0 | |
-| jmpa | 00011010 | 0 | 0 | 0 | 0 | 0 | |
-| ldi.b | 00011011 | 1 | 0 | 0 | 0 | 0 | |
-| ld.b | 00011100 | 1 | 1 | 0 | 0 | 1 | |
-| lda.b | 00011101 | 1 | 0 | 0 | 0 | 1 | |
-| st.b | 00011110 | 0 | 1 | 1 | 1 | 0 | |
-| sta.b | 00011111 | 0 | 1 | 0 | 1 | 0 | |
-| ldi.s | 00100000 | 1 | 0 | 0 | 0 | 0 | |
-| ld.s | 00100001 | 1 | 1 | 0 | 0 | 1 | |
-| lda.s | 00100010 | 1 | 1 | 0 | 0 | 1 | |
-| st.s | 00100011 | 0 | 1 | 1 | 1 | 0 | |
-| sta.s | 00100100 | 0 | 1 | 0 | 1 | 0 | |
-| jmp | 00100101 | 0 | 0 | 0 | 0 | 0 | |
-| and | 00100110 | 1 | 1 | 1 | 0 | 0 | |
-| lshr | 00100111 | 1 | 1 | 1 | 0 | 0 | |
-| ashr | 00101000 | 1 | 1 | 1 | 0 | 0 | |
-| sub.l | 00101001 | 1 | 1 | 1 | 0 | 0 | |
-| neg | 00101010 | 1 | 1 | 1 | 0 | 0 | |
-| or | 00101011 | 1 | 1 | 1 | 0 | 0 | |
-| not | 00101100 | 1 | 1 | 1 | 0 | 0 | |
-| ashr | 00101101 | 1 | 1 | 1 | 0 | 0 | |
-| xor | 00101110 | 1 | 1 | 1 | 0 | 0 | |
-| mul.l | 00101111 | 1 | 1 | 1 | 0 | 0 | |
-| swi | 00110000 | 0 | 0 | 0 | 0 | 0 | |
-| div.l | 00110001 | 1 | 1 | 1 | 0 | 0 | |
-| udiv.l | 00110010 | 1 | 1 | 1 | 0 | 0 | |
-| mod.l | 00110011 | 1 | 1 | 1 | 0 | 0 | |
-| umod.l | 00110100 | 1 | 1 | 1 | 0 | 0 | |
-| brk | 00110101 | 0 | 0 | 0 | 0 | 0 | |
-| ldo.b | 00110110 | 1 | 1 | 1 | 0 | 1 | |
-| sto.b | 00110111 | 0 | 1 | 1 | 1 | 0 | |
-| ldo.s | 00111000 | 1 | 1 | 1 | 0 | 1 | |
-| sto.s | 00111001 | 0 | 0 | 0 | 1 | 0 | |
+| nop | 00000000 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.l | 00000001 | 1 | 0 | 0 | 0 | 1 | |
+| mov | 00000010 | 1 | 0 | 1 | 0 | 0 | |
+| jsra | 00000011 | 0 | 0 | 0 | 0 | 0 | |
+| ret | 00000100 | 0 | 0 | 0 | 0 | 0 | |
+| add.l | 00000101 | 1 | 1 | 1 | 0 | 0 | |
+| push | 00000110 | 1 | 0 | 0 | 1 | 0 | |
+| pop | 00000111 | 0 | 0 | 0 | 0 | 0 | |
+| lda.l | 00001000 | 1 | 0 | 0 | 0 | 1 | |
+| sta.l | 00001001 | 0 | 1 | 0 | 1 | 0 | |
+| ld.l | 00001010 | 1 | 1 | 0 | 0 | 1 | |
+| st.l | 00001011 | 0 | 1 | 0 | 1 | 0 | |
+| ldo.l | 00001100 | 1 | 1 | 1 | 0 | 1 | |
+| sto.l | 00001101 | 0 | 1 | 1 | 1 | 0 | |
+| cmp | 00001110 | 0 | 1 | 1 | 0 | 0 | |
+| jsr | 00011001 | 0 | 1 | 0 | 0 | 0 | |
+| jmpa | 00011010 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.b | 00011011 | 1 | 0 | 0 | 0 | 0 | |
+| ld.b | 00011100 | 1 | 1 | 0 | 0 | 1 | |
+| lda.b | 00011101 | 1 | 0 | 0 | 0 | 1 | |
+| st.b | 00011110 | 0 | 1 | 1 | 1 | 0 | |
+| sta.b | 00011111 | 0 | 1 | 0 | 1 | 0 | |
+| ldi.s | 00100000 | 1 | 0 | 0 | 0 | 0 | |
+| ld.s | 00100001 | 1 | 1 | 0 | 0 | 1 | |
+| lda.s | 00100010 | 1 | 1 | 0 | 0 | 1 | |
+| st.s | 00100011 | 0 | 1 | 1 | 1 | 0 | |
+| sta.s | 00100100 | 0 | 1 | 0 | 1 | 0 | |
+| jmp | 00100101 | 0 | 0 | 0 | 0 | 0 | |
+| and | 00100110 | 1 | 1 | 1 | 0 | 0 | |
+| lshr | 00100111 | 1 | 1 | 1 | 0 | 0 | |
+| ashr | 00101000 | 1 | 1 | 1 | 0 | 0 | |
+| sub.l | 00101001 | 1 | 1 | 1 | 0 | 0 | |
+| neg | 00101010 | 1 | 1 | 1 | 0 | 0 | |
+| or | 00101011 | 1 | 1 | 1 | 0 | 0 | |
+| not | 00101100 | 1 | 1 | 1 | 0 | 0 | |
+| ashr | 00101101 | 1 | 1 | 1 | 0 | 0 | |
+| xor | 00101110 | 1 | 1 | 1 | 0 | 0 | |
+| mul.l | 00101111 | 1 | 1 | 1 | 0 | 0 | |
+| swi | 00110000 | 0 | 0 | 0 | 0 | 0 | |
+| div.l | 00110001 | 1 | 1 | 1 | 0 | 0 | |
+| udiv.l | 00110010 | 1 | 1 | 1 | 0 | 0 | |
+| mod.l | 00110011 | 1 | 1 | 1 | 0 | 0 | |
+| umod.l | 00110100 | 1 | 1 | 1 | 0 | 0 | |
+| brk | 00110101 | 0 | 0 | 0 | 0 | 0 | |
+| ldo.b | 00110110 | 1 | 1 | 1 | 0 | 1 | |
+| sto.b | 00110111 | 0 | 1 | 1 | 1 | 0 | |
+| ldo.s | 00111000 | 1 | 1 | 1 | 0 | 1 | |
+| sto.s | 00111001 | 0 | 0 | 0 | 1 | 0 | |
|--------+----------+-----+-----+-----+-----+-----+-------|
@@ -64,6 +64,7 @@ module moxie (/*AUTOARG*/
wire [0:0] fd_valid;
wire [31:0] dx_operand;
wire [31:0] dx_PC;
+ wire [31:0] xw_PC;
wire [`PCB_WIDTH-1:0] dx_pipeline_control_bits;
wire [5:0] dx_op;
wire [`PCB_WIDTH-1:0] xw_pipeline_control_bits;
@@ -178,9 +179,10 @@ module moxie (/*AUTOARG*/
.stall_o (stall_x),
.op_i (dx_op),
.PC_i (dx_PC),
+ .PC_o (xw_PC),
.operand_i (dx_operand[31:0]),
- .regA_i (rx_reg_value1),
- .regB_i (rx_reg_value2),
+ .regA_i (forward_0 ? xr_reg_result : rx_reg_value1),
+ .regB_i (forward_1 ? xr_reg_result : rx_reg_value2),
.branch_flag_o (xf_branch_flag),
.branch_target_o (xf_branch_target),
.pipeline_control_bits_i (dx_pipeline_control_bits),
@@ -198,12 +200,24 @@ module moxie (/*AUTOARG*/
cpu_write stage_write ( // Inputs
.rst_i (rst_i),
.clk_i (clk_i),
+ .PC_i (xw_PC),
.pipeline_control_bits_i (xw_pipeline_control_bits),
.memory_address_i (xw_memory_address),
.mem_result_i (xw_mem_result) );
- assign hazard_war = 0;
-
+ // Forwarding logic.
+ reg forward_0;
+ always @(posedge clk_i)
+ forward_0 <= xr_register_write_enable
+ & dx_pipeline_control_bits[`PCB_RB]
+ & (dx_register_write_index == dr_reg_index1);
+ reg forward_1;
+ always @(posedge clk_i)
+ forward_1 <= xr_register_write_enable
+ & dx_pipeline_control_bits[`PCB_RB]
+ & (dx_register_write_index == dr_reg_index2);
+
+ assign hazard_war = 0;
// assign hazard_war = dx_pipeline_control_bits[`PCB_RB] &
// xw_pipeline_control_bits[`PCB_WR] &
@@ -1,9 +1,8 @@
.text
ldi.l $sp, 0x4000000+4096
ldi.l $r0, 0x55555555
- nop
mov $r1, $sp
- mov $r2, $r0
+ mov $r2, $r1
ldi.l $r0, 0x66666666
mov $r2, $sp
nop
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