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Handle multiple simultaneous register writes

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commit de2823f444a3a66c821ce603345bcff4b7518f17 1 parent 893b122
Anthony Green authored
31 moxie/cores/moxie/cpu_decode.v
View
@@ -21,8 +21,8 @@
module cpu_decode (/*AUTOARG*/
// Outputs
- pipeline_control_bits_o, register_write_index_o, operand_o, riA_o,
- riB_o, op_o, PC_o,
+ pipeline_control_bits_o, register0_write_index_o,
+ register1_write_index_o, operand_o, riA_o, riB_o, op_o, PC_o,
// Inputs
rst_i, clk_i, stall_i, opcode_i, operand_i, valid_i, PC_i
);
@@ -41,7 +41,8 @@ module cpu_decode (/*AUTOARG*/
// --- Outputs --------------------------------------------------
output [`PCB_WIDTH-1:0] pipeline_control_bits_o;
- output [3:0] register_write_index_o;
+ output [3:0] register0_write_index_o;
+ output [3:0] register1_write_index_o;
output [31:0] operand_o;
output [3:0] riA_o;
output [3:0] riB_o;
@@ -54,7 +55,8 @@ module cpu_decode (/*AUTOARG*/
reg [31:0] operand_o;
reg [31:0] PC_o;
reg [`PCB_WIDTH-1:0] pipeline_control_bits_o;
- reg [3:0] register_write_index_o;
+ reg [3:0] register0_write_index_o;
+ reg [3:0] register1_write_index_o;
wire foo = !opcode_i[15:15];
wire [3:0] b1 = opcode_i[3:0];
@@ -76,15 +78,32 @@ module cpu_decode (/*AUTOARG*/
PC_o <= PC_i;
end
end
+
+ always @(posedge clk_i)
+ if (! stall_i) begin
+ if (opcode_i[15] == 0)
+ pipeline_control_bits_o <= control;
+ else
+ casex (opcode_i[14:11])
+ 4'b1000: // INC
+ begin
+ pipeline_control_bits_o <= 6'b101000;
+ end
+ 4'b1001: // DEC
+ begin
+ pipeline_control_bits_o <= 6'b101000;
+ end
+ endcase
+ end
always @(posedge clk_i)
begin
if (! stall_i) begin
- pipeline_control_bits_o <= control;
if (!valid_i)
op_o <= `OP_NOP;
else begin
- register_write_index_o <= riA_o;
+ register0_write_index_o <= riA_o;
+ register1_write_index_o <= riB_o;
casex (opcode_i[15:8])
8'b00000000:
begin
101 moxie/cores/moxie/cpu_execute.v
View
@@ -21,13 +21,14 @@
module cpu_execute (/*AUTOARG*/
// Outputs
- register_we_o, register_write_index_o, pipeline_control_bits_o,
- memory_address_o, reg_result_o, mem_result_o, riA_o, riB_o, PC_o,
+ register_wea_o, register_web_o, register0_write_index_o,
+ register1_write_index_o, pipeline_control_bits_o, memory_address_o,
+ reg0_result_o, reg1_result_o, mem_result_o, riA_o, riB_o, PC_o,
stall_o, branch_flag_o, branch_target_o,
// Inputs
rst_i, clk_i, stall_i, riA_i, riB_i, regA_i, regB_i,
- pipeline_control_bits_i, register_write_index_i, operand_i, op_i,
- sp_i, fp_i, PC_i
+ pipeline_control_bits_i, register0_write_index_i,
+ register1_write_index_i, operand_i, op_i, sp_i, fp_i, PC_i
);
parameter [1:0] STATE_READY = 2'b00,
@@ -46,7 +47,8 @@ module cpu_execute (/*AUTOARG*/
input [31:0] regA_i;
input [31:0] regB_i;
input [`PCB_WIDTH-1:0] pipeline_control_bits_i;
- input [3:0] register_write_index_i;
+ input [3:0] register0_write_index_i;
+ input [3:0] register1_write_index_i;
input [31:0] operand_i;
input [5:0] op_i;
input [31:0] sp_i;
@@ -54,11 +56,14 @@ module cpu_execute (/*AUTOARG*/
input [31:0] PC_i;
// --- Outputs --------------------------------------------------
- output register_we_o;
- output [3:0] register_write_index_o;
+ output register_wea_o;
+ output register_web_o;
+ output [3:0] register0_write_index_o;
+ output [3:0] register1_write_index_o;
output [`PCB_WIDTH-1:0] pipeline_control_bits_o;
output [31:0] memory_address_o;
- output [31:0] reg_result_o;
+ output [31:0] reg0_result_o;
+ output [31:0] reg1_result_o;
output [31:0] mem_result_o;
output [3:0] riA_o;
output [3:0] riB_o;
@@ -67,6 +72,8 @@ module cpu_execute (/*AUTOARG*/
output [0:0] stall_o;
reg [0:0] stall_o;
+
+ reg [31:0] CC_result;
output branch_flag_o;
output [31:0] branch_target_o;
@@ -74,10 +81,12 @@ module cpu_execute (/*AUTOARG*/
reg [0:0] branch_flag_o;
reg [31:0] branch_target_o;
- reg [3:0] register_write_index_o;
+ reg [3:0] register0_write_index_o;
+ reg [3:0] register1_write_index_o;
reg [`PCB_WIDTH-1:0] pipeline_control_bits_o;
reg [31:0] memory_address_o;
- reg [31:0] reg_result_o;
+ reg [31:0] reg0_result_o;
+ reg [31:0] reg1_result_o;
reg [31:0] mem_result_o;
reg [31:0] PC_o;
@@ -87,15 +96,18 @@ module cpu_execute (/*AUTOARG*/
assign riA_o = riA_i;
assign riB_o = riB_i;
- reg [0:0] register_we_o;
+ reg [0:0] register_wea_o;
+ reg [0:0] register_web_o;
always @(posedge rst_i or posedge clk_i)
if (rst_i == 1) begin
branch_flag_o <= 0;
current_state <= STATE_READY;
+ CC_result <= 0;
end else begin
- register_we_o = pipeline_control_bits_i[`PCB_WR];
+ register_wea_o = pipeline_control_bits_i[`PCB_WA];
+ register_web_o = pipeline_control_bits_i[`PCB_WB];
branch_flag_o <= (op_i == `OP_JMPA) || (current_state == STATE_JSR1);
current_state <= next_state;
end
@@ -119,15 +131,15 @@ module cpu_execute (/*AUTOARG*/
case (op_i)
`OP_ADD_L:
begin
- reg_result_o <= regA_i + regB_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i + regB_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_AND:
begin
- reg_result_o <= regA_i & regB_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i & regB_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -151,7 +163,7 @@ module cpu_execute (/*AUTOARG*/
end
`OP_BEQ:
begin
- $display ("Executing OP_BEQ");
+ branch_target_o <= regA_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -217,15 +229,15 @@ module cpu_execute (/*AUTOARG*/
end
`OP_CMP:
begin
- $display ("Executing OP_CMP");
+ CC_result <= regA_i - regB_i;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_DEC:
begin
// $display ("EXECUTE OP_DEC: 0x%x", operand_i);
- reg_result_o <= regA_i - operand_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i - operand_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -244,8 +256,8 @@ module cpu_execute (/*AUTOARG*/
`OP_INC:
begin
// $display ("EXECUTE OP_INC: 0x%x", operand_i);
- reg_result_o <= regA_i + operand_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i + operand_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -264,10 +276,10 @@ module cpu_execute (/*AUTOARG*/
`OP_JSR:
begin
// Decrement $sp by 8 bytes and store the return address.
- reg_result_o <= sp_i - 8;
+ reg0_result_o <= sp_i - 8;
memory_address_o <= sp_i - 8;
mem_result_o <= PC_i+6;
- register_write_index_o <= 1; // $sp
+ register0_write_index_o <= 1; // $sp
next_state <= STATE_JSR1;
stall_o <= 1;
end
@@ -310,8 +322,8 @@ module cpu_execute (/*AUTOARG*/
`OP_LDI_L:
begin
// $display ("EXECUTE OP_LDI_L: 0x%x", operand_i);
- reg_result_o <= operand_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= operand_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -366,8 +378,8 @@ module cpu_execute (/*AUTOARG*/
`OP_MOV:
begin
// $display ("Executing OP_MOV");
- reg_result_o <= regB_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regB_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -396,8 +408,8 @@ module cpu_execute (/*AUTOARG*/
end
`OP_OR:
begin
- reg_result_o <= regA_i | regB_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i | regB_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -405,18 +417,19 @@ module cpu_execute (/*AUTOARG*/
begin
// Decrement pointer register by 4 bytes.
memory_address_o <= regA_i;
- mem_result_o <= regA_i - 4;
- register_write_index_o <= register_write_index_i;
+ reg1_result_o <= regA_i - 4;
+ register0_write_index_o <= register1_write_index_i;
+ register1_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
`OP_PUSH:
begin
// Decrement pointer register by 4 bytes.
- reg_result_o <= regA_i - 4;
+ reg0_result_o <= regA_i - 4;
memory_address_o <= regA_i - 4;
mem_result_o <= regB_i;
- register_write_index_o <= register_write_index_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -424,8 +437,8 @@ module cpu_execute (/*AUTOARG*/
begin
// Increment $sp by 8
memory_address_o <= sp_i;
- reg_result_o <= sp_i + 8;
- register_write_index_o <= 1; // $sp
+ reg0_result_o <= sp_i + 8;
+ register0_write_index_o <= 1; // $sp
next_state <= STATE_RET1;
stall_o <= 0;
end
@@ -493,8 +506,8 @@ module cpu_execute (/*AUTOARG*/
end
`OP_SUB_L:
begin
- reg_result_o <= regA_i - regB_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i - regB_i;
+ register0_write_index_o <= register0_write_index_i;
next_state <= STATE_READY;
stall_o <= 0;
end
@@ -518,8 +531,8 @@ module cpu_execute (/*AUTOARG*/
end
`OP_XOR:
begin
- reg_result_o <= regA_i ^ regB_i;
- register_write_index_o <= register_write_index_i;
+ reg0_result_o <= regA_i ^ regB_i;
+ register0_write_index_o <= register0_write_index_i;
stall_o <= 0;
end
endcase // case (op_i)
@@ -527,10 +540,10 @@ module cpu_execute (/*AUTOARG*/
STATE_JSR1:
begin
// Decrement $sp by 4 bytes.
- reg_result_o <= sp_i - 4;
+ reg0_result_o <= sp_i - 4;
memory_address_o <= sp_i - 4;
mem_result_o <= fp_i;
- register_write_index_o <= 1; // $sp
+ register0_write_index_o <= 1; // $sp
branch_target_o <= operand_i;
next_state <= STATE_READY;
stall_o <= 0;
@@ -538,11 +551,11 @@ module cpu_execute (/*AUTOARG*/
STATE_RET1:
begin
// Increment $sp by 4 bytes.
- reg_result_o <= sp_i + 4;
+ reg0_result_o <= sp_i + 4;
memory_address_o <= sp_i + 4;
pipeline_control_bits_o <= 5'b10000;
// This is all wrong
- register_write_index_o <= 1; // $sp
+ register0_write_index_o <= 1; // $sp
branch_target_o <= operand_i;
next_state <= STATE_READY;
stall_o <= 0;
1  moxie/cores/moxie/cpu_ififo.v
View
@@ -108,7 +108,6 @@ module cpu_ififo #(parameter BOOT_ADDRESS = 32'h00001000
assign PC = (newPC_p_i ? PC_i : next_PC);
- // FIXME: multiple assignments to next_PC :(
always @(negedge rst_i)
next_PC <= PC_i;
28 moxie/cores/moxie/cpu_registerfile.v
View
@@ -1,6 +1,6 @@
// cpu_registerfile.v - moxie register file
//
-// Copyright (c) 2010, 2011 Anthony Green. All Rights Reserved.
+// Copyright (c) 2010, 2011, 2012 Anthony Green. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it
@@ -18,13 +18,13 @@
// 02110-1301, USA.
module cpu_registerfile (/*AUTOARG*/
- // Outputs
- value0_o, value1_o, sp_o, fp_o,
- // Inputs
- rst_i, clk_i, write_enable0_i, write_enable1_i, value0_i, value1_i,
- reg_write_index0_i, reg_write_index1_i, reg_read_index0_i,
- reg_read_index1_i
- );
+ // Outputs
+ value0_o, value1_o, sp_o, fp_o,
+ // Inputs
+ rst_i, clk_i, write_enable0_i, write_enable1_i, value0_i, value1_i,
+ reg_write_index0_i, reg_write_index1_i, reg_read_index0_i,
+ reg_read_index1_i
+ );
// synthesis translate_off
initial
@@ -45,15 +45,19 @@ module cpu_registerfile (/*AUTOARG*/
input [0:3] reg_write_index0_i, reg_write_index1_i;
input [0:3] reg_read_index0_i, reg_read_index1_i;
-
always @(posedge clk_i)
- if (write_enable0_i) begin
- $display("%x <= %x", reg_write_index0_i, value0_i);
+ begin
+ if (write_enable0_i) begin
+ $display("%x <= %x", reg_write_index0_i, value0_i);
+ end
+ if (write_enable1_i) begin
+ $display("%x <= %x", reg_write_index1_i, value1_i);
+ end
end
MEM_2w4r mem_2w4r (.clock(clk_i),
.we0(write_enable0_i),
- .we1(0),
+ .we1(write_enable1_i),
.write_addr_0(reg_write_index0_i),
.write_data_0(value0_i),
.write_addr_1(reg_write_index1_i),
6 moxie/cores/moxie/cpu_write.v
View
@@ -19,7 +19,7 @@
module cpu_write (/*AUTOARG*/
// Outputs
- register_write_index_o, register_we_o, reg_result_o,
+ register_write_index_o, register_wea_o, reg_result_o,
// Inputs
rst_i, clk_i, pipeline_control_bits_i, register_write_index_i,
memory_address_i, reg_result_i, mem_result_i, PC_i
@@ -37,13 +37,13 @@ module cpu_write (/*AUTOARG*/
output [3:0] register_write_index_o;
- output [0:0] register_we_o;
+ output [0:0] register_wea_o;
output [31:0] reg_result_o;
wire [31:0] data;
wire [3:0] register_write_index_o = register_write_index_i;
- wire [0:0] register_we_o = pipeline_control_bits_i[`PCB_WR];
+ wire [0:0] register_wea_o = pipeline_control_bits_i[`PCB_WA];
// PCB_RM is high if we are loading memory from cache
wire [31:0] reg_result_o = pipeline_control_bits_i[`PCB_RM] ? data : reg_result_i;
7 moxie/cores/moxie/defines.v
View
@@ -1,6 +1,6 @@
// defines.v - Common definitions
//
-// Copyright (c) 2010 Anthony Green. All Rights Reserved.
+// Copyright (c) 2010, 2012 Anthony Green. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it
@@ -17,8 +17,9 @@
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
// 02110-1301, USA.
-`define PCB_WIDTH 5
-`define PCB_WR 4
+`define PCB_WIDTH 6
+`define PCB_WA 5
+`define PCB_WB 4
`define PCB_RA 3
`define PCB_RB 2
`define PCB_WM 1
109 moxie/cores/moxie/microcode.org
View
@@ -3,64 +3,63 @@ Form 1 Instruction Microcode
name - instruction name
code - form 1 opcode value
-wr? - writes to register A?
+wA? - writes to register A?
+wB? - writes to register B?
rA? - reads register A?
rB? - reads register B?
wm? - writes to memory?
rm? - reads from memory?
notes - misc. comments
-|--------+----------+-----+-----+-----+-----+-----+-------|
-| name | code | wr? | rA? | rB? | wm? | rm? | notes |
-|--------+----------+-----+-----+-----+-----+-----+-------|
-| nop | 00000000 | 0 | 0 | 0 | 0 | 0 | |
-| ldi.l | 00000001 | 1 | 0 | 0 | 0 | 1 | |
-| mov | 00000010 | 1 | 0 | 1 | 0 | 0 | |
-| jsra | 00000011 | 0 | 0 | 0 | 0 | 0 | |
-| ret | 00000100 | 0 | 0 | 0 | 0 | 0 | |
-| add.l | 00000101 | 1 | 1 | 1 | 0 | 0 | |
-| push | 00000110 | 1 | 0 | 0 | 1 | 0 | |
-| pop | 00000111 | 0 | 0 | 0 | 0 | 0 | |
-| lda.l | 00001000 | 1 | 0 | 0 | 0 | 1 | |
-| sta.l | 00001001 | 0 | 1 | 0 | 1 | 0 | |
-| ld.l | 00001010 | 1 | 1 | 0 | 0 | 1 | |
-| st.l | 00001011 | 0 | 1 | 0 | 1 | 0 | |
-| ldo.l | 00001100 | 1 | 1 | 1 | 0 | 1 | |
-| sto.l | 00001101 | 0 | 1 | 1 | 1 | 0 | |
-| cmp | 00001110 | 0 | 1 | 1 | 0 | 0 | |
-| jsr | 00011001 | 0 | 1 | 0 | 0 | 0 | |
-| jmpa | 00011010 | 0 | 0 | 0 | 0 | 0 | |
-| ldi.b | 00011011 | 1 | 0 | 0 | 0 | 0 | |
-| ld.b | 00011100 | 1 | 1 | 0 | 0 | 1 | |
-| lda.b | 00011101 | 1 | 0 | 0 | 0 | 1 | |
-| st.b | 00011110 | 0 | 1 | 1 | 1 | 0 | |
-| sta.b | 00011111 | 0 | 1 | 0 | 1 | 0 | |
-| ldi.s | 00100000 | 1 | 0 | 0 | 0 | 0 | |
-| ld.s | 00100001 | 1 | 1 | 0 | 0 | 1 | |
-| lda.s | 00100010 | 1 | 1 | 0 | 0 | 1 | |
-| st.s | 00100011 | 0 | 1 | 1 | 1 | 0 | |
-| sta.s | 00100100 | 0 | 1 | 0 | 1 | 0 | |
-| jmp | 00100101 | 0 | 0 | 0 | 0 | 0 | |
-| and | 00100110 | 1 | 1 | 1 | 0 | 0 | |
-| lshr | 00100111 | 1 | 1 | 1 | 0 | 0 | |
-| ashr | 00101000 | 1 | 1 | 1 | 0 | 0 | |
-| sub.l | 00101001 | 1 | 1 | 1 | 0 | 0 | |
-| neg | 00101010 | 1 | 1 | 1 | 0 | 0 | |
-| or | 00101011 | 1 | 1 | 1 | 0 | 0 | |
-| not | 00101100 | 1 | 1 | 1 | 0 | 0 | |
-| ashr | 00101101 | 1 | 1 | 1 | 0 | 0 | |
-| xor | 00101110 | 1 | 1 | 1 | 0 | 0 | |
-| mul.l | 00101111 | 1 | 1 | 1 | 0 | 0 | |
-| swi | 00110000 | 0 | 0 | 0 | 0 | 0 | |
-| div.l | 00110001 | 1 | 1 | 1 | 0 | 0 | |
-| udiv.l | 00110010 | 1 | 1 | 1 | 0 | 0 | |
-| mod.l | 00110011 | 1 | 1 | 1 | 0 | 0 | |
-| umod.l | 00110100 | 1 | 1 | 1 | 0 | 0 | |
-| brk | 00110101 | 0 | 0 | 0 | 0 | 0 | |
-| ldo.b | 00110110 | 1 | 1 | 1 | 0 | 1 | |
-| sto.b | 00110111 | 0 | 1 | 1 | 1 | 0 | |
-| ldo.s | 00111000 | 1 | 1 | 1 | 0 | 1 | |
-| sto.s | 00111001 | 0 | 0 | 0 | 1 | 0 | |
-|--------+----------+-----+-----+-----+-----+-----+-------|
-
-
+|--------+----------+-----+-----+-----+-----+-----+-----+-------|
+| name | code | wA? | wB? | rA? | rB? | wm? | rm? | notes |
+|--------+----------+-----+-----+-----+-----+-----+-----+-------|
+| nop | 00000000 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.l | 00000001 | 1 | 0 | 0 | 0 | 0 | 1 | |
+| mov | 00000010 | 1 | 0 | 0 | 1 | 0 | 0 | |
+| jsra | 00000011 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| ret | 00000100 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| add.l | 00000101 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| push | 00000110 | 1 | 0 | 0 | 0 | 1 | 0 | |
+| pop | 00000111 | 1 | 1 | 1 | 0 | 0 | 1 | |
+| lda.l | 00001000 | 1 | 0 | 0 | 0 | 0 | 1 | |
+| sta.l | 00001001 | 0 | 0 | 1 | 0 | 1 | 0 | |
+| ld.l | 00001010 | 1 | 0 | 1 | 0 | 0 | 1 | |
+| st.l | 00001011 | 0 | 0 | 1 | 0 | 1 | 0 | |
+| ldo.l | 00001100 | 1 | 0 | 1 | 1 | 0 | 1 | |
+| sto.l | 00001101 | 0 | 0 | 1 | 1 | 1 | 0 | |
+| cmp | 00001110 | 0 | 0 | 1 | 1 | 0 | 0 | |
+| jsr | 00011001 | 0 | 0 | 1 | 0 | 0 | 0 | |
+| jmpa | 00011010 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| ldi.b | 00011011 | 1 | 0 | 0 | 0 | 0 | 0 | |
+| ld.b | 00011100 | 1 | 0 | 1 | 0 | 0 | 1 | |
+| lda.b | 00011101 | 1 | 0 | 0 | 0 | 0 | 1 | |
+| st.b | 00011110 | 0 | 0 | 1 | 1 | 1 | 0 | |
+| sta.b | 00011111 | 0 | 0 | 1 | 0 | 1 | 0 | |
+| ldi.s | 00100000 | 1 | 0 | 0 | 0 | 0 | 0 | |
+| ld.s | 00100001 | 1 | 0 | 1 | 0 | 0 | 1 | |
+| lda.s | 00100010 | 1 | 0 | 1 | 0 | 0 | 1 | |
+| st.s | 00100011 | 0 | 0 | 1 | 1 | 1 | 0 | |
+| sta.s | 00100100 | 0 | 0 | 1 | 0 | 1 | 0 | |
+| jmp | 00100101 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| and | 00100110 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| lshr | 00100111 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| ashr | 00101000 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| sub.l | 00101001 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| neg | 00101010 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| or | 00101011 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| not | 00101100 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| ashr | 00101101 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| xor | 00101110 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| mul.l | 00101111 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| swi | 00110000 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| div.l | 00110001 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| udiv.l | 00110010 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| mod.l | 00110011 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| umod.l | 00110100 | 1 | 0 | 1 | 1 | 0 | 0 | |
+| brk | 00110101 | 0 | 0 | 0 | 0 | 0 | 0 | |
+| ldo.b | 00110110 | 1 | 0 | 1 | 1 | 0 | 1 | |
+| sto.b | 00110111 | 0 | 0 | 1 | 1 | 1 | 0 | |
+| ldo.s | 00111000 | 1 | 0 | 1 | 1 | 0 | 1 | |
+| sto.s | 00111001 | 0 | 0 | 0 | 0 | 1 | 0 | |
+|--------+----------+-----+-----+-----+-----+-----+-----+-------|
2  moxie/cores/moxie/microcode.v
View
@@ -36,7 +36,7 @@ module microcode (/*AUTOARG*/
wire [`PCB_WIDTH-1:0] f1, f2;
assign f1 = rom[opcode[5:0]];
- assign f2 = 5'b11111;
+ assign f2 = 6'b111111;
assign q = (opcode[7] ? f2 : f1);
59 moxie/cores/moxie/moxie.v
View
@@ -68,14 +68,16 @@ module moxie (/*AUTOARG*/
wire [`PCB_WIDTH-1:0] dx_pipeline_control_bits;
wire [5:0] dx_op;
wire [`PCB_WIDTH-1:0] xw_pipeline_control_bits;
- wire [0:0] xr_register_write_enable;
- wire [3:0] dx_register_write_index;
- wire [3:0] xr_register_write_index;
+ wire [0:0] xr_register0_write_enable;
+ wire [0:0] xr_register1_write_enable;
+ wire [3:0] dx_register0_write_index;
+ wire [3:0] dx_register1_write_index;
+ wire [3:0] xr_register0_write_index;
+ wire [3:0] xr_register1_write_index;
wire [31:0] xw_memory_address;
- wire [31:0] xr_reg_result;
+ wire [31:0] xr_reg0_result;
+ wire [31:0] xr_reg1_result;
wire [31:0] xw_mem_result;
- wire [3:0] wr_register_write_index;
- wire [31:0] wr_reg_result;
wire [3:0] dx_regA;
wire [3:0] dx_regB;
wire [3:0] dx_regC;
@@ -96,10 +98,6 @@ module moxie (/*AUTOARG*/
reg [0:0] wb_I_stb_o;
- // Forwarding registers.
- reg forward_0;
- reg forward_1;
-
// synthesis translate_off
initial
begin
@@ -121,14 +119,15 @@ module moxie (/*AUTOARG*/
// Inputs
.rst_i (rst_i),
.clk_i (clk_i),
- .write_enable0_i (xr_register_write_enable),
- .write_enable1_i (0),
- .reg_write_index0_i (xr_register_write_index),
+ .write_enable0_i (xr_register0_write_enable),
+ .write_enable1_i (xr_register1_write_enable),
+ .reg_write_index0_i (xr_register0_write_index),
+ .reg_write_index1_i (xr_register1_write_index),
.reg_read_index0_i (dr_reg_index1),
.reg_read_index1_i (dr_reg_index2),
.sp_o (rx_sp),
.fp_o (rx_fp),
- .value0_i (xr_reg_result),
+ .value0_i (xr_reg0_result),
.value1_i (0));
always @(posedge clk_i)
@@ -143,6 +142,10 @@ module moxie (/*AUTOARG*/
assign wb_I_cyc_o = wb_I_stb_o;
+ // Forwarding logic.
+ reg forward_0;
+ reg forward_1;
+
cpu_fetch stage_fetch (// Outputs
.opcode (fd_opcode[15:0]),
.valid (fd_valid),
@@ -167,7 +170,8 @@ module moxie (/*AUTOARG*/
.stall_i (stall_x),
// Outputs
.pipeline_control_bits_o (dx_pipeline_control_bits),
- .register_write_index_o (dx_register_write_index),
+ .register0_write_index_o (dx_register0_write_index),
+ .register1_write_index_o (dx_register1_write_index),
.operand_o (dx_operand),
.PC_o (dx_PC),
.riA_o (dr_reg_index1),
@@ -183,21 +187,25 @@ module moxie (/*AUTOARG*/
.PC_i (dx_PC),
.PC_o (xw_PC),
.operand_i (dx_operand[31:0]),
- .regA_i (forward_0 ? xr_reg_result : rx_reg_value1),
- .regB_i (forward_1 ? xr_reg_result : rx_reg_value2),
+ .regA_i (forward_0 ? xr_reg0_result : rx_reg_value1),
+ .regB_i (forward_1 ? xr_reg0_result : rx_reg_value2),
.branch_flag_o (xf_branch_flag),
.branch_target_o (xf_branch_target),
.pipeline_control_bits_i (dx_pipeline_control_bits),
- .register_write_index_i (dx_register_write_index),
+ .register0_write_index_i (dx_register0_write_index),
+ .register1_write_index_i (dx_register1_write_index),
// Outputs
.pipeline_control_bits_o (xw_pipeline_control_bits),
- .register_write_index_o (xr_register_write_index),
- .reg_result_o (xr_reg_result),
+ .register0_write_index_o (xr_register0_write_index),
+ .register1_write_index_o (xr_register1_write_index),
+ .reg0_result_o (xr_reg0_result),
+ .reg1_result_o (xr_reg1_result),
.mem_result_o (xw_mem_result),
.memory_address_o (xw_memory_address),
.sp_i (rx_sp),
.fp_i (rx_fp),
- .register_we_o (xr_register_write_enable));
+ .register_wea_o (xr_register0_write_enable),
+ .register_web_o (xr_register1_write_enable));
cpu_write stage_write ( // Inputs
.rst_i (rst_i),
@@ -207,18 +215,17 @@ module moxie (/*AUTOARG*/
.memory_address_i (xw_memory_address),
.mem_result_i (xw_mem_result) );
- // Forwarding logic.
always @(posedge clk_i)
begin
// If we're writing to the same register we're about to read
// from, then forward the value we're writing back into the
// pipeline instead of reading from the register file.
- forward_0 <= xr_register_write_enable
+ forward_0 <= xr_register0_write_enable
& (dx_pipeline_control_bits[`PCB_RA]
- & (dx_register_write_index == dr_reg_index1));
- forward_1 <= xr_register_write_enable
+ & (dx_register0_write_index == dr_reg_index1));
+ forward_1 <= xr_register0_write_enable
& (dx_pipeline_control_bits[`PCB_RB]
- & (dx_register_write_index == dr_reg_index2));
+ & (dx_register0_write_index == dr_reg_index2));
end
endmodule // moxie
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