From f47a5547558c5f2811c9744308c98afd406d3070 Mon Sep 17 00:00:00 2001
From: atlas <atlas@r4780y.com>
Date: Wed, 3 Apr 2019 11:25:58 -0400
Subject: [PATCH] unittest enhancements.  my own version of a fix for the
 bytes[] problem.

---
 rflib/bits.py             |  28 +++++++++++++++++++---------
 rflib/ccspecan.py         |   3 ++-
 rflib/chipcon_nic.py      |  13 +++++++------
 rflib/chipcon_usb.py      |   3 ++-
 rflib/intelhex.py         |   7 ++++---
 tests/.test_basics.py.un~ | Bin 18883 -> 0 bytes
 tests/test_basics.py      |   7 +++++++
 tests/test_basics.py~     |  16 ----------------
 8 files changed, 41 insertions(+), 36 deletions(-)
 delete mode 100644 tests/.test_basics.py.un~
 delete mode 100644 tests/test_basics.py~

diff --git a/rflib/bits.py b/rflib/bits.py
index 5baa75e..1edcfe9 100644
--- a/rflib/bits.py
+++ b/rflib/bits.py
@@ -5,6 +5,7 @@
 from builtins import range
 from builtins import bytes
 from past.utils import old_div
+import sys
 import struct
 
 fmtsLSB = [None, "B", "<H", "<I", "<I", "<Q", "<Q", "<Q", "<Q"]
@@ -12,6 +13,15 @@
 sizes = [ 0, 1, 2, 4, 4, 8, 8, 8, 8]
 masks = [ (1<<(8*i))-1 for i in range(9) ]
 
+PYVER = int(sys.version[0])
+def correctbytes(val):
+    global PYVER
+
+    if PYVER == 2:
+        return chr(val)
+
+    return bytes([val])
+
 def wtfo(string):
     outstr = []
     bitlen = len(outstr) * 8
@@ -43,7 +53,7 @@ def strBitReverse(string):
     # convert back from MSB number to string
     out = []
     for x in range(len(string)):
-        out.append(bytes([rnum&0xff]))
+        out.append(correctbytes([rnum&0xff]))
         rnum >>= 8
     out.reverse()
     print(''.join(out).encode('hex'))
@@ -388,7 +398,7 @@ def bitSectString(string, startbit, endbit):
             mask = ~ ( (1<<diff) - 1 )
             byte &= mask
 
-        s += bytes([byte])
+        s += correctbytes([byte])
     
     ent = old_div((min(entropy)+1.0), (max(entropy)+1))
     #print "entropy: %f" % ent
@@ -481,7 +491,7 @@ def invertBits(data):
     off = 0
 
     if ldata&1:
-        output.append( bytes([ ord( data[0] ) ^ 0xff]) )
+        output.append( correctbytes( ord( data[0] ) ^ 0xff) )
         off = 1
 
     if ldata&2:
@@ -546,12 +556,12 @@ def diff_manchester_decode(data, align=False):
 
             last = (bit0 << 1) | bit1
         if (bidx & 1): 
-            out.append(bytes([obyte]))
+            out.append(correctbytes(obyte))
             obyte = 0
 
     if not (bidx & 1):
         obyte << 4 # pad 0's on end
-        out.append(bytes([obyte]))
+        out.append(correctbytes(obyte))
     return ''.join(out)
 
 
@@ -573,12 +583,12 @@ def biphase_mark_coding_encode(data):
             last = bit
         if bidx & 1:
             print("%d - write" % bidx)
-            out.append(bytes([obyte]))
+            out.append(correctbytes(obyte))
         else:
             print("%d - skip" % bidx)
     if not (bidx & 1):
         print("%d - write" % bidx)
-        out.append(bytes([obyte]))
+        out.append(correctbytes(obyte))
 
     return ''.join(out)
 
@@ -602,12 +612,12 @@ def manchester_decode(data, hilo=1):
 
             last = bit
         if (bidx & 1): 
-            out.append(bytes([obyte]))
+            out.append(correctbytes(obyte))
             obyte = 0
 
     if not (bidx & 1):
         obyte << 4 # pad 0's on end
-        out.append(bytes([obyte]))
+        out.append(correctbytes(obyte))
     return ''.join(out)
 
 def manchester_encode(data, hilo=1):
diff --git a/rflib/ccspecan.py b/rflib/ccspecan.py
index f9b5628..f6bd796 100755
--- a/rflib/ccspecan.py
+++ b/rflib/ccspecan.py
@@ -32,6 +32,7 @@
 import numpy
 import threading
 import rflib
+from .bits import correctbytes
 # import cPickle in Python 2 instead of pickle in Python 3
 if sys.version_info < (3,):
     import cPickle as pickle
@@ -415,7 +416,7 @@ def keyPressEvent(self, event):
 
         # anything else is alphanumeric
         try:
-            key= bytes([event.key()]).upper()
+            key= correctbytes(event.key()).upper()
             event.accept()
         except:
             print('Unknown key pressed: 0x%x' % event.key())
diff --git a/rflib/chipcon_nic.py b/rflib/chipcon_nic.py
index 720a327..9f69375 100644
--- a/rflib/chipcon_nic.py
+++ b/rflib/chipcon_nic.py
@@ -19,6 +19,7 @@
 import threading
 #from .chipcondefs import *
 from .chipcon_usb import *
+from .bits import correctbytes
 
 # band limits in Hz
 FREQ_MIN_300  = 281000000
@@ -443,14 +444,14 @@ def setRFRegister(self, regaddr, value, suppress=False):
             if 'suppress' the radio state (RX/TX/IDLE) is not modified
         '''
         if suppress:
-            self.poke(regaddr, bytes([value]))
+            self.poke(regaddr, correctbytes(value))
             return
             
         marcstate = self.radiocfg.marcstate
         if marcstate != MARC_STATE_IDLE:
             self.strobeModeIDLE()
             
-        self.poke(regaddr, bytes([value]))
+        self.poke(regaddr, correctbytes(value))
         
         self.strobeModeReturn(marcstate)
         #if (marcstate == MARC_STATE_RX):
@@ -1303,7 +1304,7 @@ def getAmpMode(self):
         return self.send(APP_NIC, NIC_GET_AMP_MODE, "")
 
     def setPktAddr(self, addr):
-        return self.poke(ADDR, bytes([addr]))
+        return self.poke(ADDR, correctbytes(addr))
 
     def getPktAddr(self):
         return self.peek(ADDR)
@@ -2035,9 +2036,9 @@ def setMACperiod(self, dwell_ms, mhz=24):
         t2ctl = (ord(self.peek(X_T2CTL)) & 0xfc)   | (tipidx)
         clkcon = (ord(self.peek(X_CLKCON)) & 0xc7) | (tickidx<<3)
         
-        self.poke(X_T2PR, bytes([PR]))
-        self.poke(X_T2CTL, bytes([t2ctl]))
-        self.poke(X_CLKCON, bytes([clkcon]))
+        self.poke(X_T2PR, correctbytes(PR))
+        self.poke(X_T2CTL, correctbytes(t2ctl))
+        self.poke(X_CLKCON, correctbytes(clkcon))
 
     def _setMACmode(self, _mode):
         '''
diff --git a/rflib/chipcon_usb.py b/rflib/chipcon_usb.py
index 83624bd..798215a 100644
--- a/rflib/chipcon_usb.py
+++ b/rflib/chipcon_usb.py
@@ -22,6 +22,7 @@
 from .chipcondefs import *
 from .rflib_defs import *
 from .rflib_version import *
+from .bits import correctbytes
 
 if os.name == 'nt':
     import msvcrt
@@ -957,7 +958,7 @@ def unittest(self, mhz=24):
     print(repr(self.peek(0xf000, 400)))
 
     print("\nTesting USB poke/peek")
-    data = "".join([bytes([c]) for c in range(120)])
+    data = "".join([correctbytes(c) for c in range(120)])
     where = 0xf300
     self.poke(where, data)
     ndata = self.peek(where, len(data))
diff --git a/rflib/intelhex.py b/rflib/intelhex.py
index 2f44ecb..6abc498 100644
--- a/rflib/intelhex.py
+++ b/rflib/intelhex.py
@@ -51,6 +51,7 @@
 from bisect import bisect_right
 import os
 import sys
+from .bits import correctbytes
 
 
 # the Python 2 integer types int and long have been unified in Python 3
@@ -490,7 +491,7 @@ def write_hex_file(self, f, write_start_addr=True):
         # timeit shows that using hexstr.translate(table)
         # is faster than hexstr.upper():
         # 0.452ms vs. 0.652ms (translate vs. upper)
-        table = ''.join(bytes([i]).upper() for  i in range(256))
+        table = ''.join(correctbytes(i).upper() for  i in range(256))
 
         # start address record if any
         if self.start_addr and write_start_addr:
@@ -708,7 +709,7 @@ def dump(self, tofile=None):
                     if x is not None:
                         tofile.write(' %02X' % x)
                         if 32 <= x < 128:
-                            s.append(bytes([x]))
+                            s.append(correctbytes(x))
                         else:
                             s.append('.')
                     else:
@@ -1010,7 +1011,7 @@ def _get_file_and_addr_range(s, _support_drive_letter=None):
         _support_drive_letter = (os.name == 'nt')
     drive = ''
     if _support_drive_letter:
-        if s[1:2] == ':' and s[0].upper() in ''.join([bytes([i]) for i in range(ord('A'), ord('Z')+1)]):
+        if s[1:2] == ':' and s[0].upper() in ''.join([correctbytes(i) for i in range(ord('A'), ord('Z')+1)]):
             drive = s[:2]
             s = s[2:]
     parts = s.split(':')
diff --git a/tests/.test_basics.py.un~ b/tests/.test_basics.py.un~
deleted file mode 100644
index 6710ede4c8d45ed55ce73b09b43d9133ed81d305..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/tests/test_basics.py b/tests/test_basics.py
index 44a5ead..c232caa 100644
--- a/tests/test_basics.py
+++ b/tests/test_basics.py
@@ -6,4 +6,11 @@ def test_importing(self):
         import rflib
         devs = rflib.getRfCatDevices()
         self.assertEquals(type(devs), list, "rflib.getRfCatDevices() doesn't return a list!: %r" % devs)
+        import rflib.chipcon_nic
+        import rflib.chipcon_usb
+        import rflib.chipcondefs
+        import rflib.bits
+        import rflib.ccspecan
+        import rflib.intelhex
+        import rflib.rflib_defs
 
diff --git a/tests/test_basics.py~ b/tests/test_basics.py~
deleted file mode 100644
index 32f9302..0000000
--- a/tests/test_basics.py~
+++ /dev/null
@@ -1,16 +0,0 @@
-import os
-import unittest
-
-import PE
-import vivisect.tests.helpers as helpers
-
-class RfCatBasicTests(unittest.TestCase):
-
-    def test_export_by_name(self):
-        file_path = helpers.getTestPath('windows', 'i386', 'export_by_name.dll')
-        pe = PE.peFromFileName(file_path)
-        export_list = pe.getExports()
-        self.assertEquals(len(export_list), 2, "expecting 2 exported functions")
-        self.assertEquals(export_list[0][1], 0, "exported function with ordinal 0 not found")
-        self.assertEquals(export_list[0][2], "Func1", "exported function with name 'Func1' not found")
-