{"payload":{"header_redesign_enabled":false,"results":[{"id":"221051017","archived":false,"color":"#DAE1C2","followers":3,"has_funding_file":false,"hl_name":"atmughrabi/CAPI-Precis","hl_trunc_description":"CAPIPrecis a Coherent Accelerator Processor Interface (CAPI) Abstract Layer","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":221051017,"name":"CAPI-Precis","owner_id":2029843,"owner_login":"atmughrabi","updated_at":"2021-10-22T03:11:47.791Z","has_issues":true}},"sponsorable":false,"topics":["fpga","communication","simulation","synthesis","ibm","modelsim","capi","psl","interface-design","ibm-capi","capi-precis","afu-control","shared-memory-acceleration","coherent-accelerator","pslse"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":57,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aatmughrabi%252FCAPI-Precis%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/atmughrabi/CAPI-Precis/star":{"post":"OeTpw9ayCH5UtPu5n8UqYCwPq7UvaSCK9YnGsv_OtTaqyhneSab0PZDTvVqKaToi-L9NkQu1PdgmUKsyLRmHyQ"},"/atmughrabi/CAPI-Precis/unstar":{"post":"FqWvLZDk04T3k7gSRBNUpm5ZJlaKn2uiCc93Osvsn5vayqUK8pI9tdIC1CvnaDIMfvTeC5jmegg3nGq5hga9vg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"Xu6_Eh_YxfuqCj9R1YAbJHXZS6uySwEwNonUODTqxgx_joUmQ-ecONR-1BcueQMQxM77dBms2JeRvEvfo8lXcA"}}},"title":"Repository search results"}