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Add verilog-mode dictionary.

http://www.emacswiki.org/emacs/auto-complete-verilog.el

To create the dictionary file, I copied the keywords from the above URL, removed
duplicates, added a tick mark (`) in front of the cpp keywords, and sorted the
file.
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commit 30f18ca587f47e6b34d1539a02d9ca53cb763a88 1 parent ab3dc59
@pheaver pheaver authored
Showing with 315 additions and 1 deletion.
  1. +2 −1  auto-complete.el
  2. +313 −0 dict/verilog-mode
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3  auto-complete.el
@@ -195,7 +195,8 @@
makefile-mode sh-mode fortran-mode f90-mode ada-mode
xml-mode sgml-mode
ts-mode
- sclang-mode)
+ sclang-mode
+ verilog-mode)
"Major modes `auto-complete-mode' can run on."
:type '(repeat symbol)
:group 'auto-complete)
View
313 dict/verilog-mode
@@ -0,0 +1,313 @@
+`define
+`else
+`endif
+`ifdef
+`ifndef
+`macromodule
+`module
+`primitive
+`timescale
+above
+abs
+absdelay
+ac_stim
+acos
+acosh
+alias
+aliasparam
+always
+always_comb
+always_ff
+always_latch
+analog
+analysis
+and
+asin
+asinh
+assert
+assign
+assume
+atan
+atan2
+atanh
+automatic
+before
+begin
+bind
+bins
+binsof
+bit
+branch
+break
+buf
+bufif0
+bufif1
+byte
+case
+casex
+casez
+cell
+chandle
+class
+clocking
+cmos
+config
+connectmodule
+connectrules
+const
+constraint
+context
+continue
+cos
+cosh
+cover
+covergroup
+coverpoint
+cross
+ddt
+ddx
+deassign
+default
+define
+defparam
+design
+disable
+discipline
+dist
+do
+driver_update
+edge
+else
+end
+endcase
+endclass
+endclocking
+endconfig
+endconnectrules
+enddiscipline
+endfunction
+endgenerate
+endgroup
+endif
+endinterface
+endmodule
+endnature
+endpackage
+endparamset
+endprimitive
+endprogram
+endproperty
+endsequence
+endspecify
+endtable
+endtask
+enum
+event
+exclude
+exp
+expect
+export
+extends
+extern
+final
+final_step
+first_match
+flicker_noise
+floor
+flow
+for
+force
+foreach
+forever
+fork
+forkjoin
+from
+function
+generate
+genvar
+ground
+highz0
+highz1
+hypot
+idt
+idtmod
+if
+ifdef
+iff
+ifndef
+ifnone
+ignore_bins
+illegal_bins
+import
+incdir
+include
+inf
+initial
+initial_step
+inout
+input
+inside
+instance
+int
+integer
+interface
+intersect
+join
+join_any
+join_none
+laplace_nd
+laplace_np
+laplace_zd
+laplace_zp
+large
+last_crossing
+liblist
+library
+limexp
+ln
+local
+localparam
+log
+logic
+longint
+macromodule
+mailbox
+matches
+max
+medium
+min
+modport
+module
+nand
+nand
+nature
+negedge
+net_resolution
+new
+nmos
+nmos
+noise_table
+nor
+noshowcancelled
+not
+notif0
+notif1
+null
+or
+output
+package
+packed
+parameter
+paramset
+pmos
+pmos
+posedge
+potential
+pow
+primitive
+priority
+program
+property
+protected
+pull0
+pull1
+pullup
+pulsestyle_ondetect
+pulsestyle_onevent
+pure
+rand
+randc
+randcase
+randcase
+randsequence
+rcmos
+real
+realtime
+ref
+reg
+release
+repeat
+return
+rnmos
+rpmos
+rtran
+rtranif0
+rtranif1
+scalared
+semaphore
+sequence
+shortint
+shortreal
+showcancelled
+signed
+sin
+sinh
+slew
+small
+solve
+specify
+specparam
+sqrt
+static
+string
+strong0
+strong1
+struct
+super
+supply
+supply0
+supply1
+table
+tagged
+tan
+tanh
+task
+then
+this
+throughout
+time
+timeprecision
+timer
+timescale
+timeunit
+tran
+tran
+tranif0
+tranif1
+transition
+tri
+tri
+tri0
+tri1
+triand
+trior
+trireg
+type
+typedef
+union
+unique
+unsigned
+use
+uwire
+var
+vectored
+virtual
+void
+wait
+wait_order
+wand
+weak0
+weak1
+while
+white_noise
+wildcard
+wire
+with
+within
+wor
+wreal
+xnor
+xor
+zi_nd
+zi_np
+zi_zd
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