Auto Complete in Verilog mode inserting statements #250

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ghost opened this Issue Aug 22, 2013 · 0 comments

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@ghost

Hi,

When I use auto-complete in verilog-mode, typing the first few letters of a keyword and hitting TAB (that's my trigger key) is inserting statements as if I pressed C-c C-t m (for module) etc. That means if type mod, hit TAB and select module from the menu, it is asking for the name of the module in minibuffer. This should be the case only if I pressed C-c C-t m in verilog-mode.

This behavior is seen for module, input, output, reg, wire and some other keywords.
I do not know what is causing this but I would like them not inserted when I hit TAB.

Thank you,

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