From c6295b84f4aafa62bac0eda08695c805dc417b9c Mon Sep 17 00:00:00 2001 From: Teddy van Jerry Date: Sun, 7 Apr 2024 17:23:12 +0800 Subject: [PATCH] Fix INST Parameter Format --- .gitignore | 3 +++ Cargo.lock | 2 +- Cargo.toml | 12 ++++++++++-- src/convert.rs | 2 +- src/inst.rs | 4 ++-- 5 files changed, 17 insertions(+), 6 deletions(-) diff --git a/.gitignore b/.gitignore index 47bcc6b..a07097d 100644 --- a/.gitignore +++ b/.gitignore @@ -8,3 +8,6 @@ # macOS .DS_Store + +# This Project +/private diff --git a/Cargo.lock b/Cargo.lock index db344c8..bc5d346 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -156,7 +156,7 @@ dependencies = [ [[package]] name = "pytv" -version = "0.5.2" +version = "0.5.3" dependencies = [ "clap", "regex", diff --git a/Cargo.toml b/Cargo.toml index 3be0121..4c31988 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -3,12 +3,20 @@ name = "pytv" description = "Python Templated Verilog" repository = "https://github.com/autohdw/pytv" authors = ["Teddy van Jerry "] -version = "0.5.2" +version = "0.5.3" readme = "README.md" license = "GPL-3.0-or-later" keywords = ["verilog", "python", "template", "generation"] categories = ["template-engine", "compilers", "development-tools"] -exclude = ["examples/*", "target/*", "Cargo.lock", ".github/*", ".vscode/*", ".DS_Store"] +exclude = [ + "examples/*", + "target/*", + "Cargo.lock", + ".github/*", + ".vscode/*", + ".DS_Store", + "private/*", +] edition = "2021" [features] diff --git a/src/convert.rs b/src/convert.rs index 94c46a9..2372918 100644 --- a/src/convert.rs +++ b/src/convert.rs @@ -281,7 +281,7 @@ impl Convert { " s = [' .%s(%s)' % tuple for tuple in tuples]\n", " return ('' if first_port else ',\\n') + ',\\n'.join(s)\n\n", "def _verilog_vparams_var_map(tuples, first_vparam):\n", - " s = ['\\n parameter %s = %s' % tuple for tuple in tuples]\n", + " s = ['\\n .%s(%s)' % tuple for tuple in tuples]\n", " return ('#(' if first_vparam else ',') + ','.join(s)\n", ), self.output_inst_file_name() diff --git a/src/inst.rs b/src/inst.rs index 353afc2..c115bdb 100644 --- a/src/inst.rs +++ b/src/inst.rs @@ -140,7 +140,7 @@ impl Convert { } else { writeln!( stream, - "print(f'{}\\n parameter {} = {}', end='')", + "print(f'{}\\n .{}({})', end='')", if first_vparam { first_vparam = false; "#(" @@ -161,7 +161,7 @@ impl Convert { } } if !first_vparam { - writeln!(stream, "print(f')')")?; + writeln!(stream, "print(')')")?; } match inst_map["name"].as_str() { Some(name) => writeln!(