irqchip: Add RISC-V incoming MSI controller driver

The RISC-V advanced interrupt architecture specification introduces
a new MSI controller for managing MSIs on RISC-V platform. This new
MSI controller is referred to as incoming message signaled interrupt
controller (IMSIC) which manages MSI on per-HART basis.
(For more details refer https://github.com/riscv/riscv-aia)

This patch adds an irqchip driver for IMSIC chip found on RISC-V
platforms.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

drivers/irqchip/Kconfig

@@ -29,7 +29,6 @@ config ARM_GIC_V2M
 
 config GIC_NON_BANKED
 	bool
-
 config ARM_GIC_V3
 	bool
 	select IRQ_DOMAIN_HIERARCHY
@@ -544,6 +543,25 @@ config RISCV_APLIC
 
 	   If you don't know what to do here, say Y.
 
+config RISCV_IMSIC
+	bool "Incoming MSI Controller"
+	depends on RISCV
+	select IRQ_DOMAIN_HIERARCHY
+	select GENERIC_MSI_IRQ_DOMAIN
+	help
+	   This enables support for the IMSIC chip found in RISC-V systems.
+	   The IMSIC controls message signaled interrupts and forwards them
+	   to each core as wired local interrupt.
+
+	   If you don't know what to do here, say Y.
+
+config RISCV_IMSIC_PCI
+	bool
+	depends on RISCV_IMSIC
+	depends on PCI
+	depends on PCI_MSI
+	default RISCV_IMSIC
+
 config EXYNOS_IRQ_COMBINER
 	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
 	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST

drivers/irqchip/Makefile

@@ -100,6 +100,7 @@ obj-$(CONFIG_RISCV_INTC)		+= irq-riscv-intc.o
 obj-$(CONFIG_RISCV_ACLINT_SWI)		+= irq-riscv-aclint-swi.o
 obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
 obj-$(CONFIG_RISCV_APLIC)		+= irq-riscv-aplic.o
+obj-$(CONFIG_RISCV_IMSIC)		+= irq-riscv-imsic.o
 obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
 obj-$(CONFIG_IMX_INTMUX)		+= irq-imx-intmux.o
 obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o