Why is there alignment in the LLVM datalayout? #64
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On StackOverflow, user tofro writes in his answer:
I'd like to try compiling LLVM/rustc with 8-bit alignment through and through and see how it goes. @dylanmckay, do you have a ticket # or a repro description or anything on the problems you've encountered that triggered the above commit? |
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As a test, I've now recompiled |
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Most of the alignment stuff has been untouched since I originally imported the old SVN repository from SourceForge. I haven't dealt with it much and so my knowledge is pretty poor. Safest to assume that if something looks intentional, it probably isn't
From memory, I think any atomic-related code would trigger it. I think the related issue is avr-llvm/llvm#214. |
(avr-rust/rust-legacy-fork#63 avr-rust/rust-legacy-fork#64) [AVR] Use 1-byte alignment for all data types (avr-rust/rust-legacy-fork#64)
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I have now pushed the changes on both the LLVM and the Rust side that turn off all alignment. |
(avr-rust/rust-legacy-fork#63 avr-rust/rust-legacy-fork#64) [AVR] Use 1-byte alignment for all data types (avr-rust/rust-legacy-fork#64)
This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi.
This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314179 91177308-0d34-0410-b5e6-96231b3b80d8
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My |
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Committed in r314179 |
This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314179 91177308-0d34-0410-b5e6-96231b3b80d8
This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi.
------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314379 91177308-0d34-0410-b5e6-96231b3b80d8
------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. ------------------------------------------------------------------------ llvm-svn=314379
------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. ------------------------------------------------------------------------
------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. ------------------------------------------------------------------------
------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. ------------------------------------------------------------------------ llvm-svn=314379
------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. ------------------------------------------------------------------------ llvm-svn: 314379
This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 avr-rust/rust-legacy-fork#64 Patch By Gergo Erdi. llvm-svn: 314179
I've tracked down a bug to bad alignment here: #63 (comment) After a lot of pain, I've found out that there is actually a hardcoded datalayout in the AVR backend, in
AVRTargetMachine.cpp, taking precedence over whatever the user puts in the LLVM IR file. This datalayout is currently as follows:Expanded, the above states:
To my untrained eye, this looks completely bogus (except, yeah, pointers are 2 bytes:)), so I did a quick
git blamein the hope that I'd find a good reason. There is a commit which gives an explanation for the 2-byte alignment:but it still doesn't explain what's going on with the 4- and even 8-byte alignments (which were also introduced in the same commit). The original code is already missing an
aspecifier, so that's probably just an oversight/typo.If we need 2-byte alignment for >=2 byte words as the above commit states, what's the reason for going above that for wider types, that are going to be soft-implemented anyway?
Would this work instead? It would certainly fix #63
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