Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
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AWSaalluri and kristopk Rc v1 4 (#413)
* adding shell v1.4
	new file:   shell_v04261818/build/constraints/cl_clocks_aws.xdc
	new file:   shell_v04261818/build/constraints/cl_ddr.xdc
	new file:   shell_v04261818/build/constraints/cl_debug_bridge.xdc
	new file:   shell_v04261818/build/constraints/cl_synth_aws.xdc
	new file:   shell_v04261818/build/constraints/xsdbm_timing_exception.xdc
	new file:   shell_v04261818/build/scripts/apply_debug_constraints.tcl
	new file:   shell_v04261818/build/scripts/aws_build_dcp_from_cl.sh
	new file:   shell_v04261818/build/scripts/aws_clock_properties.tcl
	new file:   shell_v04261818/build/scripts/aws_dcp_verify.tcl
	new file:   shell_v04261818/build/scripts/aws_gen_clk_constraints.tcl
	new file:   shell_v04261818/build/scripts/check_uram.tcl
	new file:   shell_v04261818/build/scripts/device_type.tcl
	new file:   shell_v04261818/build/scripts/params.tcl
	new file:   shell_v04261818/build/scripts/prepare_build_environment.sh
	new file:   shell_v04261818/build/scripts/step_user.tcl
	new file:   shell_v04261818/build/scripts/strategy_BASIC.tcl
	new file:   shell_v04261818/build/scripts/strategy_CONGESTION.tcl
	new file:   shell_v04261818/build/scripts/strategy_DEFAULT.tcl
	new file:   shell_v04261818/build/scripts/strategy_EXPLORE.tcl
	new file:   shell_v04261818/build/scripts/strategy_TIMING.tcl
	new file:   shell_v04261818/build/scripts/uram_options.tcl
	new file:   shell_v04261818/build/scripts/vivado_keyfile.txt
	new file:   shell_v04261818/build/scripts/vivado_keyfile_2017_4.txt
	new file:   shell_v04261818/build/scripts/vivado_vhdl_keyfile.txt
	new file:   shell_v04261818/build/scripts/vivado_vhdl_keyfile_2017_4.txt
	new file:   shell_v04261818/design/interfaces/README.md
	new file:   shell_v04261818/design/interfaces/cl_ports.vh
	new file:   shell_v04261818/design/interfaces/unused_apppf_irq_template.inc
	new file:   shell_v04261818/design/interfaces/unused_cl_sda_template.inc
	new file:   shell_v04261818/design/interfaces/unused_ddr_a_b_d_template.inc
	new file:   shell_v04261818/design/interfaces/unused_ddr_c_template.inc
	new file:   shell_v04261818/design/interfaces/unused_dma_pcis_template.inc
	new file:   shell_v04261818/design/interfaces/unused_flr_template.inc
	new file:   shell_v04261818/design/interfaces/unused_pcim_template.inc
	new file:   shell_v04261818/design/interfaces/unused_sh_bar1_template.inc
	new file:   shell_v04261818/design/interfaces/unused_sh_ocl_template.inc
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.veo
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.vho
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.xci
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.xml
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0_clocks.xdc
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0_ooc.xdc
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/doc/axi_clock_converter_v2_1_changelog.txt
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/axi_infrastructure_v1_1_0.vh
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/axi_infrastructure_v1_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.vhd
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/simulation/fifo_generator_vlog_beh.v
	new file:   shell_v04261818/design/ip/axi_clock_converter_0/synth/axi_clock_converter_0.v
	new file:   shell_v04261818/design/ip/axi_register_slice/axi_register_slice.veo
	new file:   shell_v04261818/design/ip/axi_register_slice/axi_register_slice.vho
	new file:   shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xci
	new file:   shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xml
	new file:   shell_v04261818/design/ip/axi_register_slice/doc/axi_register_slice_v2_1_changelog.txt
	new file:   shell_v04261818/design/ip/axi_register_slice/hdl/axi_infrastructure_v1_1_0.vh
	new file:   shell_v04261818/design/ip/axi_register_slice/hdl/axi_infrastructure_v1_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/axi_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/axi_register_slice/sim/axi_register_slice.v
	new file:   shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v
	new file:   shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.veo
	new file:   shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.vho
	new file:   shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xci
	new file:   shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xml
	new file:   shell_v04261818/design/ip/axi_register_slice_light/doc/axi_register_slice_v2_1_changelog.txt
	new file:   shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_0.vh
	new file:   shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/axi_register_slice_light/sim/axi_register_slice_light.v
	new file:   shell_v04261818/design/ip/axi_register_slice_light/synth/axi_register_slice_light.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect.bd
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect.bxml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect.dcp
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_sim_netlist.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_sim_netlist.vhdl
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_stub.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_stub.vhdl
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/hdl/cl_axi_interconnect_wrapper.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/hw_handoff/cl_axi_interconnect.hwh
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/hw_handoff/cl_axi_interconnect_bd.tcl
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/sim/cl_axi_interconnect_m00_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/synth/cl_axi_interconnect_m00_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/sim/cl_axi_interconnect_m01_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/synth/cl_axi_interconnect_m01_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/sim/cl_axi_interconnect_m02_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/synth/cl_axi_interconnect_m02_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/cl_axi_interconnect_m03_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/cl_axi_interconnect_m03_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/cl_axi_interconnect_m03_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/sim/cl_axi_interconnect_m03_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/synth/cl_axi_interconnect_m03_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/cl_axi_interconnect_s00_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/cl_axi_interconnect_s00_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/cl_axi_interconnect_s00_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/sim/cl_axi_interconnect_s00_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/synth/cl_axi_interconnect_s00_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/cl_axi_interconnect_s01_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/cl_axi_interconnect_s01_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/cl_axi_interconnect_s01_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/sim/cl_axi_interconnect_s01_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/synth/cl_axi_interconnect_s01_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/cl_axi_interconnect_xbar_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/cl_axi_interconnect_xbar_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/cl_axi_interconnect_xbar_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/sim/cl_axi_interconnect_xbar_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/synth/cl_axi_interconnect_xbar_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/3ed1/hdl/axi_register_slice_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/5c35/hdl/fifo_generator_v13_2_rfs.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/5c35/hdl/fifo_generator_v13_2_rfs.vhd
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/5c35/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/5c35/simulation/fifo_generator_vlog_beh.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/67d8/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/9909/hdl/axi_data_fifo_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/c631/hdl/axi_crossbar_v2_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/sim/cl_axi_interconnect.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/synth/cl_axi_interconnect.hwdef
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/synth/cl_axi_interconnect.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect/ui/bd_26ef0651.ui
	new file:   shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xci
	new file:   shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml
	new file:   shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/sim/cl_axi_interconnect_m00_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/synth/cl_axi_interconnect_m00_regslice_0.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/.Xil/Vivado-60721-ip-10-206-21-243/coregen/clock_temp/clock_temp.xci
	new file:   shell_v04261818/design/ip/cl_debug_bridge/.Xil/Vivado-60721-ip-10-206-21-243/coregen/clock_temp/clock_temp.xml
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/bd_a493.bd
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/bd_a493.bxml
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/bd_a493_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/hw_handoff/cl_debug_bridge.hwh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/hw_handoff/cl_debug_bridge_bd.tcl
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/bd_a493_xsdbm_0.xci
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/bd_a493_xsdbm_0.xml
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/bd_a493_xsdbm_0_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/constraints/xsdbm.xdc
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/ltlib_v1_0_0_ver.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_core.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_i2x.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_icn.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_id_map.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_in.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/synth/bd_a493_xsdbm_0.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_1/bd_a493_lut_buffer_0.xci
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_1/bd_a493_lut_buffer_0.xml
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_1/synth/bd_a493_lut_buffer_0.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/sim/bd_a493.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/synth/bd_a493.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/bd_0/synth/cl_debug_bridge.hwdef
	new file:   shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge.veo
	new file:   shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge.vho
	new file:   shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge.xci
	new file:   shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge.xml
	new file:   shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge_ooc.xdc
	new file:   shell_v04261818/design/ip/cl_debug_bridge/doc/debug_bridge_v3_0_changelog.txt
	new file:   shell_v04261818/design/ip/cl_debug_bridge/sim/cl_debug_bridge.v
	new file:   shell_v04261818/design/ip/cl_debug_bridge/synth/cl_debug_bridge.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/bd_bf3f.bd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/bd_bf3f.bmm
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/bd_bf3f.bxml
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/bd_bf3f_ooc.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/hdl/bd_bf3f_wrapper.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/hw_handoff/ddr4_core_microblaze_mcs.hwh
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/hw_handoff/ddr4_core_microblaze_mcs_bd.tcl
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_0/bd_bf3f_microblaze_I_0.xci
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_0/data/mb_bootloop_le.elf
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_0/hdl/microblaze_v10_0_vh_rfs.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_0/sim/bd_bf3f_microblaze_I_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_0/synth/bd_bf3f_microblaze_I_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_1/bd_bf3f_rst_0_0.xci
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_1/bd_bf3f_rst_0_0_board.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_1/hdl/lib_cdc_v1_0_rfs.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_10/hdl/iomodule_v3_1_vh_rfs.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_10/synth/bd_bf3f_iomodule_0_0.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_3/synth/bd_bf3f_dlmb_0.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_4/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_4/synth/bd_bf3f_dlmb_cntlr_0.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_5/synth/bd_bf3f_ilmb_cntlr_0.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/bd_bf3f_lmb_bram_I_0.xml
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/bd_bf3f_lmb_bram_I_0_ooc.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/sim/bd_bf3f_lmb_bram_I_0.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/simulation/blk_mem_gen_v8_4.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/synth/bd_bf3f_lmb_bram_I_0.vhd
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	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_7/bd_bf3f_second_dlmb_cntlr_0.xml
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_7/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_7/sim/bd_bf3f_second_dlmb_cntlr_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_7/synth/bd_bf3f_second_dlmb_cntlr_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_8/bd_bf3f_second_ilmb_cntlr_0.xci
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_8/bd_bf3f_second_ilmb_cntlr_0.xml
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_8/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_8/sim/bd_bf3f_second_ilmb_cntlr_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_8/synth/bd_bf3f_second_ilmb_cntlr_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/bd_bf3f_second_lmb_bram_I_0.xci
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/bd_bf3f_second_lmb_bram_I_0.xml
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/bd_bf3f_second_lmb_bram_I_0_ooc.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/sim/bd_bf3f_second_lmb_bram_I_0.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/simulation/blk_mem_gen_v8_4.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/synth/bd_bf3f_second_lmb_bram_I_0.vhd
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/sim/bd_bf3f.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/synth/bd_bf3f.v
	new file:   shell_v04261818/design/ip/ddr4_core/bd_0/synth/ddr4_core_microblaze_mcs.hwdef
	new file:   shell_v04261818/design/ip/ddr4_core/ddr4_core.veo
	new file:   shell_v04261818/design/ip/ddr4_core/ddr4_core.vho
	new file:   shell_v04261818/design/ip/ddr4_core/ddr4_core.xci
	new file:   shell_v04261818/design/ip/ddr4_core/ddr4_core.xml
	new file:   shell_v04261818/design/ip/ddr4_core/ddr4_core_board.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/doc/ddr4_v2_2_changelog.txt
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/ddr4_core_microblaze_mcs.xci
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/ddr4_core_microblaze_mcs.xml
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/ddr4_core_microblaze_mcs_board.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/ddr4_core_microblaze_mcs_ooc.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/mb_bootloop_le.elf
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/sim/ddr4_core_microblaze_mcs.v
	new file:   shell_v04261818/design/ip/ddr4_core/ip_0/synth/ddr4_core_microblaze_mcs.v
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/ddr4_core_phy.xci
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/ddr4_core_phy.xml
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/par/ddr4_core_phy_ooc.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/ip_top/ddr4_core_phy.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/map/ddr4_core_phy_ddrMapDDR4.vh
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/map/ddr4_core_phy_iobMapDDR4.vh
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/map/ddr4_core_phy_riuMap.vh
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/phy/ddr4_core_phy_ddr4.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv
	new file:   shell_v04261818/design/ip/ddr4_core/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv
	new file:   shell_v04261818/design/ip/ddr4_core/par/ddr4_core.xdc
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_a_upsizer.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_ar_channel.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_aw_channel.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_b_channel.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_cmd_arbiter.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_cmd_fsm.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_cmd_translator.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_fifo.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_incr_cmd.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_r_channel.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_register_slice.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_upsizer.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_w_channel.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_wr_cmd_fsm.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axi_wrap_cmd.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_axic_register_slice.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_carry_and.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_carry_latch_and.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_carry_latch_or.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_carry_or.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_command_fifo.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_comparator.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_comparator_sel.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_comparator_sel_static.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_r_upsizer.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi/ddr4_v2_2_w_upsizer.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_addr_decode.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_read.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_reg.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_reg_bank.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_top.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_write.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_core_ddr4_cal_riu.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_3_cal_assert.vh
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_3_chipscope_icon2xsdb_mstrbr_ver_inc.vh
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_3_cs_ver_inc.vh
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal.sv
	new file:   shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_addr_decode.sv
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	new file:   shell_v04261818/hlx/build/scripts/tclapp/xilinx/faasutils/keyfile_v2.txt
	new file:   shell_v04261818/hlx/build/scripts/tclapp/xilinx/faasutils/keyfile_v2_vhd.txt
	new file:   shell_v04261818/hlx/build/scripts/tclapp/xilinx/faasutils/make_faas.tcl
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	new file:   shell_v04261818/hlx/build/scripts/tclapp/xilinx/faasutils/sed/IPI_template/faas_project.tcl
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	new file:   shell_v04261818/hlx/build/scripts/tclapp/xilinx/faasutils/subprocs.tcl
	new file:   shell_v04261818/hlx/build/scripts/tclapp/xilinx/faasutils/yellow_cloud.png
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	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/bd/bd.tcl
	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/component.xml
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	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/doc/aws_v1_0_changelog.txt
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	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/ip/axi_clock_converter_0/axi_clock_converter_0.xci
	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/ip/ddr4_core/ddr4_core.xci
	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/ttcl/clocks_xdc.ttcl
	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/ttcl/ooc_xdc.ttcl
	new file:   shell_v04261818/hlx/design/ip/aws_v1_0/xgui/aws_v1_0.tcl
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/component.xml
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/constraints/dds_ooc.xdc
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/doc/ReleaseNotes.txt
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/data/dds.mdd
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/data/dds.tcl
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/src/Makefile
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/src/xdds.c
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/src/xdds.h
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/src/xdds_hw.h
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/src/xdds_linux.c
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/drivers/dds_v1_0/src/xdds_sinit.c
	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/hdl/verilog/dds.v
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	new file:   shell_v04261818/hlx/design/ip/dds_v1_0/xgui/dds_v1_0.tcl
	new file:   shell_v04261818/hlx/design/lib/cl_ports_hlx.vh
	new file:   shell_v04261818/hlx/design/lib/cl_top.sv
	new file:   shell_v04261818/hlx/design/lib/sh_connectors.vh
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/cl_hello_world_ref.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/constraints/cl_pnr_user.xdc
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/constraints/cl_synth_user.xdc
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/design.xml
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/design/hello_world.v
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/faas_project.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/init.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/params.tcl
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	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_hls_dds/constraints/cl_pnr_user.xdc
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	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/cl_ipi_cdma_test.tcl
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	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/init.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/params.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/software/Makefile
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/software/test_cl.c
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	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/faas_project.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/hello_world.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/init.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/params.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/software/Makefile
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/software/test_cl.c
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/supported_parts_boards.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/verif/test_cl.sv
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_dram_dma/cl_dram_dma.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_dram_dma/design.xml
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_dram_dma/faas_project.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_dram_dma/init.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_dram_dma/params.tcl
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	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/cl_hello_world.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/design.xml
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/faas_project.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/init.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/params.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/supported_parts_boards.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/verif/scripts/dpi.tcl
	new file:   shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/verif/scripts/dpi_xsim.tcl
	new file:   shell_v04261818/hlx/hlx_setup.tcl
	new file:   shell_v04261818/hlx/verif/cl_ports_sh_bfm.vh
	new file:   shell_v04261818/hlx/verif/scripts/dpi.tcl
	new file:   shell_v04261818/hlx/verif/scripts/dpi_xsim.tcl
	new file:   shell_v04261818/hlx/verif/tb.sv
	new file:   shell_v04261818/hlx/verif/test_cl.sv
	new file:   shell_v04261818/new_cl_template/build/README.md
	new file:   shell_v04261818/new_cl_template/build/constraints/cl_pnr_user.xdc
	new file:   shell_v04261818/new_cl_template/build/constraints/cl_synth_user.xdc
	new file:   shell_v04261818/new_cl_template/build/scripts/aws_build_dcp_from_cl.sh
	new file:   shell_v04261818/new_cl_template/build/scripts/create_dcp_from_cl.tcl
	new file:   shell_v04261818/new_cl_template/build/scripts/encrypt.tcl
	new file:   shell_v04261818/new_cl_template/build/scripts/synth_cl_hello_world.tcl
	new file:   shell_v04261818/new_cl_template/design/cl_template.sv
	new file:   shell_v04261818/new_cl_template/design/cl_template_defines.vh
	new file:   shell_v04261818/shell_version.txt

* removing v1.3 shell

* merging shell V1.4 updates to public

* updating xilinx/SDAccel_examples to latest on aws_2017.1 branch

* fixing merge issues

* document updates
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README.md

Table of Contents

  1. Overview of AWS EC2 FPGA Development Kit
  2. Getting Started
  3. FPGA Developer AMI available on AWS Marketplace
  4. FPGA Hardware Development Kit (HDK)
  5. FPGA Software Development Kit (SDK)
  6. OpenCL Development Environment with Amazon EC2 F1 FPGA Instances to accelerate your C/C++ applications
  7. Developer Support
  8. Recommended Documentation
  9. Github tips and tricks

Overview of AWS EC2 FPGA Development Kit

The AWS EC2 FPGA Development Kit is provided by AWS to support development and runtime on AWS FPGA instances. Amazon EC2 FPGA instances are high-performance compute instances with field programmable gate arrays (FPGAs) that are programmed to create custom hardware accelerations in EC2. F1 instances are easy to program and AWS provides everything needed to develop, simulate, debug, compile and run hardware accelerated applications. Using the FPGA developer AMI, developers create an FPGA design. Once the FPGA design (also called CL - Custom logic) is complete, developers create the Amazon FPGA Image (AFI), and deploy it to the F1 instance in just a few clicks. AFIs are reusable, shareable and can be deployed in a scalable and secure way. Alt text

Overview of Development Environments

Development Environment Description Accelerator Language Development Tool Debug Options Typical Developer / FPGA Experience
Software Defined Accelerator Development - SDAccel Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances C/C++/OpenCL, Verilog/VHDL (RTL) SDx/Vivado (GUI or scipt) SW/HW Emulation, Simulation, GDB, Virtual JTAG (Chipscope) SW or HW Developer with zero FPGA experience
Hardware Accelerator Development - HDK Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances Verilog/VHDL Vivado Simulation, Virtual JTAG HW Developer with advanced FPGA experience
IP Integrator or High Level Synthesis (HLx) Graphical interface development experience for integrating IP and high level synthesis development Verilog/VHDL/C Vivado (GUI) Simulation, Virtual JTAG HW Developer with intermediate FPGA experience

Overview of Runtime Environments

Runtime Environment Hardware Interface Host Code Language FPGA Tools