diff --git a/hdk/common/shell_v071417d3/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/sim/cl_axi_interconnect_s01_regslice_0.v b/hdk/common/shell_v071417d3/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/sim/cl_axi_interconnect_s01_regslice_0.v new file mode 100644 index 000000000..3e178f5e2 --- /dev/null +++ b/hdk/common/shell_v071417d3/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/sim/cl_axi_interconnect_s01_regslice_0.v @@ -0,0 +1,411 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_register_slice:2.1 +// IP Revision: 12 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module cl_axi_interconnect_s01_regslice_0 ( + aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awregion, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arregion, + s_axi_arqos, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) +input wire [5 : 0] s_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) +input wire [63 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) +input wire [7 : 0] s_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) +input wire [2 : 0] s_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) +input wire [1 : 0] s_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) +input wire [0 : 0] s_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) +input wire [3 : 0] s_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) +input wire [2 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) +input wire [3 : 0] s_axi_awregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) +input wire [3 : 0] s_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) +input wire s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) +output wire s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) +input wire [511 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) +input wire [63 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) +input wire s_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) +input wire s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) +output wire s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) +output wire [5 : 0] s_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) +output wire [1 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) +output wire s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) +input wire s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) +input wire [5 : 0] s_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) +input wire [63 : 0] s_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) +input wire [7 : 0] s_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) +input wire [2 : 0] s_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) +input wire [1 : 0] s_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) +input wire [0 : 0] s_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) +input wire [3 : 0] s_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) +input wire [2 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) +input wire [3 : 0] s_axi_arregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) +input wire [3 : 0] s_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) +input wire s_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) +output wire s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) +output wire [5 : 0] s_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) +output wire [511 : 0] s_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) +output wire [1 : 0] s_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) +output wire s_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) +output wire s_axi_rvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) +input wire s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) +output wire [5 : 0] m_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [63 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) +output wire [7 : 0] m_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) +output wire [2 : 0] m_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) +output wire [1 : 0] m_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) +output wire [0 : 0] m_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) +output wire [3 : 0] m_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) +output wire [3 : 0] m_axi_awregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) +output wire [3 : 0] m_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [511 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [63 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) +output wire m_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) +input wire [5 : 0] m_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) +output wire [5 : 0] m_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) +output wire [63 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) +output wire [7 : 0] m_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) +output wire [2 : 0] m_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) +output wire [1 : 0] m_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) +output wire [0 : 0] m_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) +output wire [3 : 0] m_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) +output wire [3 : 0] m_axi_arregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) +output wire [3 : 0] m_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) +output wire m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) +input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) +input wire [5 : 0] m_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) +input wire [511 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) +input wire m_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) +input wire m_axi_rvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) +output wire m_axi_rready; + + axi_register_slice_v2_1_12_axi_register_slice #( + .C_FAMILY("virtexuplus"), + .C_AXI_PROTOCOL(0), + .C_AXI_ID_WIDTH(6), + .C_AXI_ADDR_WIDTH(64), + .C_AXI_DATA_WIDTH(512), + .C_AXI_SUPPORTS_USER_SIGNALS(0), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_WUSER_WIDTH(1), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_REG_CONFIG_AW(7), + .C_REG_CONFIG_W(1), + .C_REG_CONFIG_B(7), + .C_REG_CONFIG_AR(7), + .C_REG_CONFIG_R(1) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awregion(s_axi_awregion), + .s_axi_awqos(s_axi_awqos), + .s_axi_awuser(1'H0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), + .s_axi_wid(6'H00), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), + .s_axi_wuser(1'H0), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(s_axi_arid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arlen(s_axi_arlen), + .s_axi_arsize(s_axi_arsize), + .s_axi_arburst(s_axi_arburst), + .s_axi_arlock(s_axi_arlock), + .s_axi_arcache(s_axi_arcache), + .s_axi_arprot(s_axi_arprot), + .s_axi_arregion(s_axi_arregion), + .s_axi_arqos(s_axi_arqos), + .s_axi_aruser(1'H0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arready(s_axi_arready), + .s_axi_rid(s_axi_rid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(s_axi_rlast), + .s_axi_ruser(), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .m_axi_awid(m_axi_awid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awlock(m_axi_awlock), + .m_axi_awcache(m_axi_awcache), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(m_axi_awregion), + .m_axi_awqos(m_axi_awqos), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'H0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arlock(m_axi_arlock), + .m_axi_arcache(m_axi_arcache), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(m_axi_arregion), + .m_axi_arqos(m_axi_arqos), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(m_axi_rid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(m_axi_rlast), + .m_axi_ruser(1'H0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule