diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index e9a2fe3241687..060806eaf8d69 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -141,6 +141,8 @@
 
 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 #define MAX_SCLK_OUT		50000000
+/* max sclk of driver strength 4mA */
+#define IO_DRIVER_4MA_MAX_SCLK_OUT	24000000
 
 enum rockchip_ssi_type {
 	SSI_MOTO_SPI = 0,
@@ -191,6 +193,7 @@ struct rockchip_spi {
 	struct sg_table rx_sg;
 	struct rockchip_spi_dma_data dma_rx;
 	struct rockchip_spi_dma_data dma_tx;
+	struct pinctrl_state *high_speed_state;
 };
 
 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
@@ -537,6 +540,19 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
 	div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 	div = (div + 1) & 0xfffe;
 
+	/*
+	 * If speed is larger than IO_DRIVER_4MA_MAX_SCLK_OUT,
+	 * set higher driver strength.
+	 */
+	if (rs->high_speed_state) {
+		if (rs->speed > IO_DRIVER_4MA_MAX_SCLK_OUT)
+			pinctrl_select_state(rs->dev->pins->p,
+					     rs->high_speed_state);
+		else
+			pinctrl_select_state(rs->dev->pins->p,
+					     rs->dev->pins->default_state);
+	}
+
 	/* Rx sample delay is expressed in parent clock cycles (max 3) */
 	rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 				1000000000 >> 8);
@@ -759,6 +775,13 @@ static int rockchip_spi_probe(struct platform_device *pdev)
 		master->dma_rx = rs->dma_rx.ch;
 	}
 
+	rs->high_speed_state = pinctrl_lookup_state(rs->dev->pins->p,
+						     "high_speed");
+	if (IS_ERR_OR_NULL(rs->high_speed_state))
+		dev_warn(&pdev->dev, "no high_speed pinctrl state\n");
+	else
+		rs->high_speed_state = NULL;
+
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register master\n");