From 956d6fc4e0fe22ed412ece19b9d98fd032a0cbf8 Mon Sep 17 00:00:00 2001 From: Kamil Trzcinski Date: Tue, 15 Aug 2017 11:08:38 +0200 Subject: [PATCH] Add rk3328-gmac support --- arch/arm/dts/rk3328-evb.dts | 87 ++++++++++ arch/arm/dts/rk3328.dtsi | 19 ++ .../include/asm/arch-rockchip/grf_rk3328.h | 164 ++++++++++++++++++ configs/evb-rk3328_defconfig | 11 ++ configs/evb-rk3399_defconfig | 4 + drivers/clk/rockchip/clk_rk3328.c | 31 ++++ drivers/net/designware.c | 7 +- drivers/net/gmac_rockchip.c | 94 ++++++++++ drivers/pinctrl/rockchip/pinctrl_rk3328.c | 160 +++++++++++++++++ include/configs/rk3328_common.h | 13 +- include/dt-bindings/clock/rk3328-cru.h | 8 +- 11 files changed, 590 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 8a14c653e46..01b3dd2826f 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -15,6 +15,20 @@ stdout-path = &uart2; }; + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + vcc3v3_sdmmc: sdmmc-pwren { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; @@ -87,3 +101,76 @@ vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; }; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + /* SPI DMA does not work currently */ + /delete-property/ dmas; + /delete-property/ #dma-cells; + /delete-property/ dma-names; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <1>; + compatible = "st,m25p128", "spi-flash"; + reg = <0x0>; + spi-max-frequency = <25000000>; + status = "okay"; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + system@0 { + label = "system"; + reg = <0x0 0x8000>; + read-only; + }; + + loader@8000 { + label = "loader"; + reg = <0x8000 0x3F8000>; + }; + + reserved@400000 { + label = "reserved"; + reg = <0x400000 0x3C0000>; + read-only; + }; + + vendor@7c0000 { + label = "vendor"; + reg = <0x7C0000 0x40000>; + }; + + uboot@800000 { + label = "uboot"; + reg = <0x800000 0x400000>; + }; + + atf@c00000 { + label = "atf"; + reg = <0xC00000 0x400000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 0bab1e33ccd..5de1059aa29 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -456,6 +456,25 @@ status = "disabled"; }; + gmac2io: ethernet@ff540000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff540000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, + <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, + <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, + <&cru PCLK_MAC2IO>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC2IO_A>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h index f0a0781d8db..a396510d558 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -145,6 +145,74 @@ enum { GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, GPIO0A7_EMMC_DATA0 = 2, + GPIO0B0_SEL_SHIFT = 0, + GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT, + GPIO0B0_MAC_TXCLK = 1, + + GPIO0B1_SEL_SHIFT = 2, + GPIO0B1_SEL_MASK = 3 << GPIO0B1_SEL_SHIFT, + GPIO0B1_MAC_CRS = 1, + + GPIO0B2_SEL_SHIFT = 4, + GPIO0B2_SEL_MASK = 3 << GPIO0B2_SEL_SHIFT, + GPIO0B2_MAC_RXCLK = 1, + + GPIO0B3_SEL_SHIFT = 6, + GPIO0B3_SEL_MASK = 3 << GPIO0B3_SEL_SHIFT, + GPIO0B3_MAC_MDIO = 1, + + GPIO0B4_SEL_SHIFT = 8, + GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT, + GPIO0B4_MAC_TXEN = 1, + + GPIO0B6_SEL_SHIFT = 12, + GPIO0B6_SEL_MASK = 3 << GPIO0B6_SEL_SHIFT, + GPIO0B6_MAC_RXD1 = 1, + + GPIO0B7_SEL_SHIFT = 14, + GPIO0B7_SEL_MASK = 3 << GPIO0B7_SEL_SHIFT, + GPIO0B7_MAC_RXD0 = 1, + + GPIO0C0_SEL_SHIFT = 0, + GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT, + GPIO0C0_MAC_TXD1 = 1, + + GPIO0C1_SEL_SHIFT = 2, + GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT, + GPIO0C1_MAC_TXD0 = 1, + + GPIO0C2_SEL_SHIFT = 4, + GPIO0C2_SEL_MASK = 3 << GPIO0C2_SEL_SHIFT, + GPIO0C2_MAC_COL = 1, + + GPIO0C3_SEL_SHIFT = 6, + GPIO0C3_SEL_MASK = 3 << GPIO0C3_SEL_SHIFT, + GPIO0C3_MAC_MDC = 1, + + GPIO0C4_SEL_SHIFT = 8, + GPIO0C4_SEL_MASK = 3 << GPIO0C4_SEL_SHIFT, + GPIO0C4_MAC_RXD3 = 1, + + GPIO0C5_SEL_SHIFT = 10, + GPIO0C5_SEL_MASK = 3 << GPIO0C5_SEL_SHIFT, + GPIO0C5_MAC_RXD2 = 1, + + GPIO0C6_SEL_SHIFT = 12, + GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT, + GPIO0C6_MAC_TXD2 = 1, + + GPIO0C7_SEL_SHIFT = 14, + GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT, + GPIO0C7_MAC_TXD3 = 1, + + GPIO0D0_SEL_SHIFT = 0, + GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT, + GPIO0D0_MAC_CLK = 1, + + GPIO0D1_SEL_SHIFT = 2, + GPIO0D1_SEL_MASK = 3 << GPIO0D1_SEL_SHIFT, + GPIO0D1_MAC_RXDV = 1, + /* GPIO0D_IOMUX*/ GPIO0D6_SEL_SHIFT = 12, GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, @@ -156,6 +224,77 @@ enum { GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, + /* GPIO1B_IOMUX */ + GPIO1B0_SEL_SHIFT = 0, + GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT, + GPIO1B0_MAC_TXD1 = 2, + + GPIO1B1_SEL_SHIFT = 2, + GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT, + GPIO1B1_MAC_TXD0 = 2, + + GPIO1B2_SEL_SHIFT = 4, + GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT, + GPIO1B2_MAC_RXD1 = 2, + + GPIO1B3_SEL_SHIFT = 6, + GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT, + GPIO1B3_MAC_RXD0 = 2, + + GPIO1B4_SEL_SHIFT = 8, + GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT, + GPIO1B4_MAC_TXCLK = 2, + + GPIO1B5_SEL_SHIFT = 10, + GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT, + GPIO1B5_MAC_RXCLK = 2, + + GPIO1B6_SEL_SHIFT = 12, + GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT, + GPIO1B6_MAC_RXD3 = 2, + + GPIO1B7_SEL_SHIFT = 14, + GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT, + GPIO1B7_MAC_RXD2 = 2, + + /* GPIO1C_IOMUX */ + GPIO1C0_SEL_SHIFT = 0, + GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT, + GPIO1C0_MAC_TXD3 = 2, + + GPIO1C1_SEL_SHIFT = 2, + GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT, + GPIO1C1_MAC_TXD2 = 2, + + GPIO1C2_SEL_SHIFT = 4, + GPIO1C2_SEL_MASK = 3 << GPIO1C2_SEL_SHIFT, + GPIO1C2_MAC_CRS = 2, + + GPIO1C3_SEL_SHIFT = 6, + GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT, + GPIO1C3_MAC_MDIO = 2, + + GPIO1C4_SEL_SHIFT = 8, + GPIO1C4_SEL_MASK = 3 << GPIO1C4_SEL_SHIFT, + GPIO1C4_MAC_COL = 2, + + GPIO1C5_SEL_SHIFT = 10, + GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT, + GPIO1C5_MAC_CLK = 2, + + GPIO1C6_SEL_SHIFT = 12, + GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT, + GPIO1C6_MAC_RXDV = 2, + + GPIO1C7_SEL_SHIFT = 14, + GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT, + GPIO1C7_MAC_MDC = 2, + + /* GPIO1D_IOMUX */ + GPIO1D1_SEL_SHIFT = 2, + GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT, + GPIO1D1_MAC_TXEN = 2, + /* GPIO2A_IOMUX */ GPIO2A0_SEL_SHIFT = 0, GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, @@ -245,4 +384,29 @@ enum { IOMUX_SEL_SDMMC_M1, }; +#ifndef GPIO_BIAS_MASK +/* GPIO Bias settings */ +enum GPIO_BIAS { + GPIO_BIAS_2MA = 0, + GPIO_BIAS_4MA, + GPIO_BIAS_8MA, + GPIO_BIAS_12MA, +}; + +#define GPIO_BIAS_MASK 0x3 +#define GPIO_BIAS_SHIFT(x) ((x) * 2) +#endif + +#ifndef GPIO_PULL_MASK +enum GPIO_PU_PD { + GPIO_PULL_NORMAL = 0, + GPIO_PULL_UP, + GPIO_PULL_DOWN, + GPIO_PULL_REPEAT, +}; + +#define GPIO_PULL_MASK 0x3 +#define GPIO_PULL_SHIFT(x) ((x) * 2) +#endif + #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 8ccff8705e2..a899b0f0971 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -19,14 +19,23 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3328=y CONFIG_REGULATOR_PWM=y @@ -37,6 +46,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -55,3 +65,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x2207 CONFIG_G_DNL_PRODUCT_NUM=0x330a CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y +CONFIG_CMD_ETHSW=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 55757d2f732..8456a8e4da6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -70,3 +70,7 @@ CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y +CONFIG_MTD=y +CONFIG_ST_SMI=y +CONFIG_MTD_PARTITIONS=y +CONFIG_FLASH_CFI_LEGACY=y diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index c3a6650de03..e2ac84188fe 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -478,6 +479,30 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) return DIV_TO_RATE(GPLL_HZ, div); } +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static ulong rk3328_gmac_set_clk(struct rk3328_cru *cru, + ulong clk_id, ulong set_rate) +{ + struct rk3328_grf_regs *grf; + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + switch (clk_id) { + case SCLK_MAC2IO: + rk_clrsetreg(&grf->mac_con[1], BIT(10), BIT(10)); + break; + + case SCLK_MAC2IO_EXT: + rk_clrsetreg(&grf->soc_con[4], BIT(14), BIT(14)); + break; + + default: + return -EINVAL; + } + + return set_rate; +} +#endif + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -531,6 +556,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case SCLK_MAC2IO: + case SCLK_MAC2IO_EXT: + ret = rk3328_gmac_set_clk(priv->cru, clk->id, rate); + break; +#endif default: return -ENOENT; } diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 521e4dde41f..6205c55d08a 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -667,8 +667,9 @@ int designware_eth_probe(struct udevice *dev) ret = device_get_supply_regulator(dev, "phy-supply", &phy_supply); + printf("phy-supply: %d\n", ret); if (ret) { - debug("%s: No phy supply\n", dev->name); + printf("%s: No phy supply\n", dev->name); } else { ret = regulator_set_enable(phy_supply, true); if (ret) { @@ -693,7 +694,7 @@ int designware_eth_probe(struct udevice *dev) } #endif - debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); + printf("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); ioaddr = iobase; priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); @@ -704,7 +705,7 @@ int designware_eth_probe(struct udevice *dev) priv->bus = miiphy_get_dev_by_name(dev->name); ret = dw_phy_init(priv, dev); - debug("%s, ret=%d\n", __func__, ret); + printf("%s, ret=%d\n", __func__, ret); return ret; } diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 586ccbff0a7..7e45d7d5ca0 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -84,6 +85,37 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } +static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3328_grf_regs *grf; + int clk; + enum { + RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, + RK3328_GMAC_CLK_SEL_25M = 3 << 11, + RK3328_GMAC_CLK_SEL_125M = 0 << 11, + RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3328_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3328_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3328_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); + return 0; +} + static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3368_grf *grf; @@ -162,6 +194,61 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), + RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + + RK3328_GMAC_RMII_MODE_MASK = BIT(9), + RK3328_GMAC_RMII_MODE_DISABLE = 0, + RK3328_GMAC_RMII_MODE_ENABLE = BIT(9), + }; + enum { + RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), + RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), + RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), + RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), + RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 7, + RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), + RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0, + RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), + }; + enum { + RK3328_GMAC_IO_SEL_MASK = BIT(2), + RK3328_GMAC_IO_SEL_M1 = BIT(2), + + RK3328_GMAC_M1_CH_SELECT_MASK = BIT(10), + RK3328_GMAC_M1_CH_SELECT_M1 = 0, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3328_GMAC_PHY_INTF_SEL_MASK | + RK3328_RXCLK_DLY_ENA_GMAC_MASK | + RK3328_TXCLK_DLY_ENA_GMAC_MASK | + RK3328_GMAC_RMII_MODE_MASK, + RK3328_GMAC_PHY_INTF_SEL_RGMII | + RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3328_TXCLK_DLY_ENA_GMAC_ENABLE | + RK3328_GMAC_RMII_MODE_DISABLE); + + rk_clrsetreg(&grf->mac_con[0], + RK3328_CLK_RX_DL_CFG_GMAC_MASK | + RK3328_CLK_TX_DL_CFG_GMAC_MASK, + pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); + + rk_clrsetreg(&grf->com_iomux, + RK3328_GMAC_IO_SEL_MASK | + RK3328_GMAC_M1_CH_SELECT_MASK, + RK3328_GMAC_IO_SEL_M1 | + RK3328_GMAC_M1_CH_SELECT_M1); +} + static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3368_grf *grf; @@ -279,6 +366,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = { .set_to_rgmii = rk3288_gmac_set_to_rgmii, }; +const struct rk_gmac_ops rk3328_gmac_ops = { + .fix_mac_speed = rk3328_gmac_fix_mac_speed, + .set_to_rgmii = rk3328_gmac_set_to_rgmii, +}; + const struct rk_gmac_ops rk3368_gmac_ops = { .fix_mac_speed = rk3368_gmac_fix_mac_speed, .set_to_rgmii = rk3368_gmac_set_to_rgmii, @@ -292,6 +384,8 @@ const struct rk_gmac_ops rk3399_gmac_ops = { static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, + { .compatible = "rockchip,rk3328-gmac", + .data = (ulong)&rk3328_gmac_ops }, { .compatible = "rockchip,rk3368-gmac", .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index c74163e026a..9c9150be0c8 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -200,6 +200,157 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, } } +static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id) +{ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B0_SEL_MASK | + GPIO1B1_SEL_MASK | + GPIO1B2_SEL_MASK | + GPIO1B4_SEL_MASK | + GPIO1B5_SEL_MASK | + GPIO1B6_SEL_MASK | + GPIO1B7_SEL_MASK, + GPIO1B0_MAC_TXD1 << GPIO1B0_SEL_SHIFT | + GPIO1B1_MAC_TXD0 << GPIO1B1_SEL_SHIFT | + GPIO1B2_MAC_RXD1 << GPIO1B2_SEL_SHIFT | + GPIO1B3_MAC_RXD0 << GPIO1B3_SEL_SHIFT | + GPIO1B4_MAC_TXCLK << GPIO1B4_SEL_SHIFT | + GPIO1B5_MAC_RXCLK << GPIO1B5_SEL_SHIFT | + GPIO1B6_MAC_RXD3 << GPIO1B6_SEL_SHIFT | + GPIO1B7_MAC_RXD2 << GPIO1B7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1b_p, + GPIO1B0_SEL_MASK | + GPIO1B1_SEL_MASK | + GPIO1B2_SEL_MASK | + GPIO1B4_SEL_MASK | + GPIO1B5_SEL_MASK | + GPIO1B6_SEL_MASK | + GPIO1B7_SEL_MASK, + GPIO_PULL_NORMAL << GPIO1B0_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B1_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B2_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B3_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B4_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B5_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B6_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1B7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1b_e, + GPIO1B0_SEL_MASK | + GPIO1B1_SEL_MASK | + GPIO1B2_SEL_MASK | + GPIO1B4_SEL_MASK | + GPIO1B5_SEL_MASK | + GPIO1B6_SEL_MASK | + GPIO1B7_SEL_MASK, + GPIO_BIAS_12MA << GPIO1B0_SEL_SHIFT | + GPIO_BIAS_12MA << GPIO1B1_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1B2_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1B3_SEL_SHIFT | + GPIO_BIAS_12MA << GPIO1B4_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1B5_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1B6_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1B7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C0_SEL_MASK | + GPIO1C1_SEL_MASK | + GPIO1C3_SEL_MASK | + GPIO1C5_SEL_MASK | + GPIO1C6_SEL_MASK | + GPIO1C7_SEL_MASK, + GPIO1C0_MAC_TXD3 << GPIO1C0_SEL_SHIFT | + GPIO1C1_MAC_TXD2 << GPIO1C1_SEL_SHIFT | + GPIO1C3_MAC_MDIO << GPIO1C3_SEL_SHIFT | + GPIO1C5_MAC_CLK << GPIO1C5_SEL_SHIFT | + GPIO1C6_MAC_RXDV << GPIO1C6_SEL_SHIFT | + GPIO1C7_MAC_MDC << GPIO1C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1c_p, + GPIO1C0_SEL_MASK | + GPIO1C1_SEL_MASK | + GPIO1C3_SEL_MASK | + GPIO1C5_SEL_MASK | + GPIO1C6_SEL_MASK | + GPIO1C7_SEL_MASK, + GPIO_PULL_NORMAL << GPIO1C0_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1C1_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1C3_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1C5_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1C6_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO1C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1c_e, + GPIO1C0_SEL_MASK | + GPIO1C1_SEL_MASK | + GPIO1C2_SEL_MASK | + GPIO1C3_SEL_MASK | + GPIO1C4_SEL_MASK | + GPIO1C5_SEL_MASK | + GPIO1C6_SEL_MASK | + GPIO1C7_SEL_MASK, + GPIO_BIAS_12MA << GPIO1C0_SEL_SHIFT | + GPIO_BIAS_12MA << GPIO1C1_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1C2_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1C3_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1C4_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1C5_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1C6_SEL_SHIFT | + GPIO_BIAS_2MA << GPIO1C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D1_SEL_MASK, + GPIO1D1_MAC_TXEN << GPIO1D1_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1d_p, + GPIO1D1_SEL_MASK, 0); + + rk_clrsetreg(&grf->gpio1d_e, + GPIO1D1_SEL_MASK, + GPIO_BIAS_12MA << GPIO1D1_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0b_iomux, + GPIO0B0_SEL_MASK | + GPIO0B4_SEL_MASK, + GPIO0B0_MAC_TXCLK << GPIO0B0_SEL_SHIFT | + GPIO0B4_MAC_TXEN << GPIO0B4_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0b_p, + GPIO0B0_SEL_MASK | + GPIO0B4_SEL_MASK, + GPIO_PULL_NORMAL << GPIO0B0_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO0B4_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0c_iomux, + GPIO0C0_SEL_MASK | + GPIO0C1_SEL_MASK | + GPIO0C6_SEL_MASK | + GPIO0C7_SEL_MASK, + GPIO0C0_MAC_TXD1 << GPIO0C0_SEL_SHIFT | + GPIO0C1_MAC_TXD0 << GPIO0C1_SEL_SHIFT | + GPIO0C6_MAC_TXD2 << GPIO0C6_SEL_SHIFT | + GPIO0C7_MAC_TXD3 << GPIO0C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0c_p, + GPIO0C0_SEL_MASK | + GPIO0C1_SEL_MASK | + GPIO0C6_SEL_MASK | + GPIO0C7_SEL_MASK, + GPIO_PULL_NORMAL << GPIO0C0_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO0C1_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO0C6_SEL_SHIFT | + GPIO_PULL_NORMAL << GPIO0C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D0_SEL_MASK, + GPIO0D0_MAC_CLK << GPIO0D0_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0d_p, + GPIO0D0_SEL_MASK, + GPIO_PULL_NORMAL << GPIO0D0_SEL_SHIFT); +} + static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); @@ -236,6 +387,11 @@ static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3328_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3328_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -270,6 +426,10 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_SDCARD; case 14: return PERIPH_ID_EMMC; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 24: + return PERIPH_ID_GMAC; +#endif } return -ENOENT; diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 906c821aeff..6604587d291 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -38,7 +38,7 @@ #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH 1 #define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 @@ -63,4 +63,15 @@ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +/* enable usb config for usb ether */ +#define CONFIG_USB_HOST_ETHER + +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_ASIX88179 +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_RTL8152 + #endif diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index 6d8bf1330ba..068f179498c 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -86,6 +86,9 @@ #define SCLK_USB3OTG_SUSPEND 97 #define SCLK_REF_USB3OTG_SRC 98 #define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 /* dclk gates */ #define DCLK_LCDC 180 @@ -199,10 +202,7 @@ #define CLK_NR_CLKS (HCLK_HDCP + 1) -#define SCLK_MAC2IO 0 -#define SCLK_MAC2PHY 1 - -#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1) +#define CLKGRF_NR_CLKS (0) /* soft-reset indices */ #define SRST_CORE0_PO 0