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Added support for reading/writing ARM7TDMI ICE registers
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azonenberg committed Jul 20, 2018
1 parent 2a36739 commit 21823e2
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Showing 3 changed files with 112 additions and 97 deletions.
90 changes: 63 additions & 27 deletions ARM7TDMISProcessor.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -55,40 +55,76 @@ ARM7TDMISProcessor::ARM7TDMISProcessor(
: ARMDevice(idcode, iface, pos)
, m_rev(rev)
{
//LogTrace("Found ARM7TDMI-S processor at %08x, probing...\n", address);
m_irlength = 4;
m_selectedChain = 255;

/*
//Read the Debug ID register and extract flags
m_deviceID.word = ReadRegisterByIndex(DBGDIDR);
m_breakpoints = m_deviceID.bits.bpoints_minus_one + 1;
m_context_breakpoints = m_deviceID.bits.context_bpoints_minus_one + 1;
m_watchpoints = m_deviceID.bits.wpoints_minus_one + 1;
m_hasDevid = m_deviceID.bits.has_dbgdevid;
m_hasSecExt = m_deviceID.bits.sec_ext;
m_hasSecureHalt = m_deviceID.bits.sec_ext && !m_deviceID.bits.no_secure_halt;
m_revision = m_deviceID.bits.revision;
m_variant = m_deviceID.bits.variant;
if(m_deviceID.bits.pcsr_legacy_addr)
m_pcsrIndex = DBGPCSR_LEGACY;
else
m_pcsrIndex = DBGPCSR;
//Verify the CPU is powered up
uint32_t powerdown_status = ReadRegisterByIndex(DBGPRSR);
LogTrace("DBGPRSR = %08x\n", powerdown_status);
if(!powerdown_status & 1)
{
WriteRegisterByIndex(DBGPRCR, 0x00000008); //Power up the CPU
powerdown_status = ReadRegisterByIndex(DBGPRSR);
LogTrace("DBGPRSR = %08x\n", powerdown_status);
}*/
//WriteIceRegister(DEBUG_CTRL, 0x3f);
//uint32_t ret = ReadIceRegister(DEBUG_CTRL);
}

ARM7TDMISProcessor::~ARM7TDMISProcessor()
{

}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Scan chain selection

void ARM7TDMISProcessor::SelectScanChain(uint8_t n)
{
//Don't select the chain again if it's alreadty active
if(m_selectedChain == n)
return;

uint8_t inst = SCAN_N;
SetIR(&inst);
ScanDR(&n, NULL, 4);

m_selectedChain = n;
}

void ARM7TDMISProcessor::WriteIceRegister(uint8_t reg, uint32_t value)
{
//Prepare to send data to the correct chain
SelectIceRTChain();
uint8_t inst = INTEST;
SetIR(&inst);

uint8_t wdata[5] =
{
static_cast<uint8_t>((value >> 0) & 0xff),
static_cast<uint8_t>((value >> 8) & 0xff),
static_cast<uint8_t>((value >> 16) & 0xff),
static_cast<uint8_t>((value >> 24) & 0xff),
static_cast<uint8_t>(0x20 | reg)
};

ScanDR(wdata, NULL, 38);
}

uint32_t ARM7TDMISProcessor::ReadIceRegister(uint8_t reg)
{
//Prepare to send data to the correct chain
SelectIceRTChain();
uint8_t inst = INTEST;
SetIR(&inst);

uint8_t wdata[5] =
{
0x00,
0x00,
0x00,
0x00,
reg
};

uint8_t rdata[5] = {0};
ScanDR(wdata, NULL, 38);
ScanDR(wdata, rdata, 38);

return (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | rdata[0];
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// General device info

Expand Down Expand Up @@ -176,7 +212,7 @@ void ARM7TDMISProcessor::PrintIDRegister(ARM7TDMISDebugIDRegister did)
"reserved 7",
"reserved 8",
"reserved 9",
"reserved a",
"reserved a"
"reserved b",
"reserved c",
"reserved d",
Expand Down
113 changes: 43 additions & 70 deletions ARM7TDMISProcessor.h
Original file line number Diff line number Diff line change
Expand Up @@ -57,88 +57,59 @@ class ARM7TDMISProcessor : public DebuggableDevice
size_t pos);
virtual ~ARM7TDMISProcessor();

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Registers
/*
//register numbers, multiply by 4 to get address
enum ARM_V7M_SCS_REGISTERS
//JTAG instructions
enum JTAG_INSTRUCTIONS
{
ACTLR = 0x0002, //Auxiliary Control Register
STCSR = 0x0004, //SysTick Control/Status Register
STRVR = 0x0005, //SysTick Reload Value Register
STCVR = 0x0006, //SysTick Current Value Register
STCR = 0x0007, //SysTick Calibration Value Register
CPUID = 0x0340, //CPU identifier
ICSR = 0x0341, //Interrupt Control and State Register
VTOR = 0x0342, //Vector Table Offset Register
AIRCR = 0x0343, //Application Interrupt and Reset Control Register
SCR = 0x0344, //System Control Register
CCR = 0x0345, //Configuration and Control Register
SHPR1 = 0x0346, //System Handler Priority Register 1
SHPR2 = 0x0347, //System Handler Priority Register 2
SHPR3 = 0x0348, //System Handler Priority Register 3
SHCSR = 0x0349, //System Handler Control and State Register
CFSR = 0x034a, //Configurable Fault Status Register
HFSR = 0x034b, //Hard Fault Status Register
DFSR = 0x034c, //Debug Fault Status Register
MMFAR = 0x034d, //MemManage Address Register
BFAR = 0x034e, //BusFault Address Register
AFSR = 0x034f, //Auxiliary Fault Status Register
ID_PFR0 = 0x0350, //Processor Feature Register 0
ID_PFR1 = 0x0351, //Processor Feature Register 1
ID_DFR0 = 0x0352, //Debug Features Register 0
ID_AFR0 = 0x0353, //Auxiliary Features Register 0
ID_MMFR0 = 0x0354, //Memory Model Features Register 0
ID_MMFR1 = 0x0355, //Memory Model Features Register 1
ID_MMFR2 = 0x0356, //Memory Model Features Register 2
ID_MMFR3 = 0x0357, //Memory Model Features Register 3
ID_ISAR0 = 0x0358, //Instruction Set Attributes Register 0
ID_ISAR1 = 0x0359, //Instruction Set Attributes Register 1
ID_ISAR2 = 0x035a, //Instruction Set Attributes Register 2
ID_ISAR3 = 0x035b, //Instruction Set Attributes Register 3
ID_ISAR4 = 0x035c, //Instruction Set Attributes Register 4
CPACR = 0x0362, //Coprocessor Access Control Register
DHCSR = 0x037c, //Debug Halting Control/Status Register
DCRSR = 0x037d, //Debug Core Register Selector
DCRDR = 0x037e, //Debug Core Register Data Register
DEMCR = 0x037f, //Debug Exception Monitor Control Register
STIR = 0x03c0 //Software Triggered Interrupt Register
SCAN_N = 0x2,
RESTART = 0x4,
INTEST = 0xc,
IDCODE = 0xe,
BYPASS = 0xf
};

//register numbers for DCRSR
enum ARM_V7M_CPU_REGISTERS
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal debug stuff

protected:

enum IceRegisters
{
R0 = 0,
R1 = 1,
R2 = 2,
R3 = 3,
R4 = 4,
R5 = 5,
R6 = 6,
R7 = 7,
R8 = 8,
R9 = 9,
R10 = 10,
R11 = 11,
R12 = 12,
SP = 13, //current stack pointer
LR = 14, //link register
DBGRA = 15, //debug return address
XPSR = 16, //flags etc
MSP = 17, //main SP
PSP = 18, //process SP
CTRL = 20 //{CONTROL, FAULTMASK, BASEPRI, PRIMASK}
DEBUG_CTRL = 0x00,
DEBUG_STAT = 0x01,
DCC_CTRL = 0x04,
DCC_DATA = 0x05,
WATCH0_ADDR = 0x08,
WATCH0_AMASK = 0x09,
WATCH0_DATA = 0x0a,
WATCH0_DMASK = 0x0b,
WATCH0_CTRL = 0x0c,
WATCH0_CMASK = 0x0d,
WATCH1_ADDR = 0x10,
WATCH1_AMASK = 0x11,
WATCH1_DATA = 0x12,
WATCH1_DMASK = 0x13,
WATCH1_CTRL = 0x14,
WATCH1_CMASK = 0x15
};
*/

void SelectScanChain(uint8_t n);

void SelectDebugChain()
{ SelectScanChain(1); }

void SelectIceRTChain()
{ SelectScanChain(2); }

void WriteIceRegister(uint8_t reg, uint32_t value);
uint32_t ReadIceRegister(uint8_t reg);

public:
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// General device info

virtual std::string GetDescription();
virtual void PrintInfo();
/*
bool HaltedDueToUnrecoverableException();
void DumpRegisters();
*/

Expand Down Expand Up @@ -199,6 +170,8 @@ class ARM7TDMISProcessor : public DebuggableDevice
*/

unsigned int m_rev;

unsigned int m_selectedChain;
};

#endif
Expand Down
6 changes: 6 additions & 0 deletions JtagDevice.h
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,12 @@ class JtagDevice

public:
//JTAG interface helpers
void SetIR(const unsigned char* data)
{ SetIR(data, m_irlength); }

void SetIRDeferred(const unsigned char* data)
{ SetIRDeferred(data, m_irlength); }

void SetIR(const unsigned char* data, int count);
void SetIRDeferred(const unsigned char* data, int count);
void SetIR(const unsigned char* data, unsigned char* data_out, int count);
Expand Down

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