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Lots of refactoring of ARM CoreSight classes
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/*********************************************************************************************************************** | ||
* * | ||
* ANTIKERNEL v0.1 * | ||
* * | ||
* Copyright (c) 2012-2018 Andrew D. Zonenberg * | ||
* All rights reserved. * | ||
* * | ||
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the * | ||
* following conditions are met: * | ||
* * | ||
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the * | ||
* following disclaimer. * | ||
* * | ||
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the * | ||
* following disclaimer in the documentation and/or other materials provided with the distribution. * | ||
* * | ||
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products * | ||
* derived from this software without specific prior written permission. * | ||
* * | ||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * | ||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * | ||
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * | ||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * | ||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * | ||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * | ||
* POSSIBILITY OF SUCH DAMAGE. * | ||
* * | ||
***********************************************************************************************************************/ | ||
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/** | ||
@file | ||
@author Andrew D. Zonenberg | ||
@brief Base class for ARM CoreSight components on a debug APB bus | ||
*/ | ||
#include "jtaghal.h" | ||
#include "ARMAPBDevice.h" | ||
#include "ARMCoreSightDevice.h" | ||
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using namespace std; | ||
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ARMCoreSightDevice::ARMCoreSightDevice(ARMDebugMemAccessPort* ap, uint32_t address, ARMDebugPeripheralIDRegisterBits idreg) | ||
: ARMAPBDevice(ap, address, idreg) | ||
{ | ||
} | ||
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ARMCoreSightDevice::~ARMCoreSightDevice() | ||
{ | ||
} | ||
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void ARMCoreSightDevice::PrintInfo() | ||
{ | ||
LogVerbose("%s rev %d.%d.%d\n", | ||
GetDescription().c_str(), | ||
m_idreg.revnum, m_idreg.cust_mod, m_idreg.revand); | ||
} | ||
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string ARMCoreSightDevice::GetDescription() | ||
{ | ||
switch(m_idreg.partnum) | ||
{ | ||
case 0x906: | ||
return "CoreSight Cross Trigger Interface"; | ||
case 0x907: | ||
return "CoreSight Embedded Trace Buffer"; | ||
case 0x908: | ||
return "CoreSight Trace Funnel"; | ||
case 0x912: | ||
return "CoreSight Trace Port Interface Unit"; | ||
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//ID is 913, not 914. CoreSight Components TRM is wrong. | ||
//See ARM #TAC650738 | ||
case 0x913: | ||
return "CoreSight Instrumentation Trace Macrocell"; | ||
case 0x914: | ||
return "CoreSight Serial Wire Output"; | ||
case 0x950: | ||
return "Cortex-A9 Program Trace Macrocell"; | ||
case 0x9A0: | ||
return "Cortex-A9 Performance Monitoring Unit"; | ||
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default: | ||
LogWarning("Unknown ARM device (part number 0x%x)\n", m_idreg.partnum); | ||
return "unknown CoreSight device"; | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,49 @@ | ||
/*********************************************************************************************************************** | ||
* * | ||
* ANTIKERNEL v0.1 * | ||
* * | ||
* Copyright (c) 2012-2018 Andrew D. Zonenberg * | ||
* All rights reserved. * | ||
* * | ||
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the * | ||
* following conditions are met: * | ||
* * | ||
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the * | ||
* following disclaimer. * | ||
* * | ||
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the * | ||
* following disclaimer in the documentation and/or other materials provided with the distribution. * | ||
* * | ||
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products * | ||
* derived from this software without specific prior written permission. * | ||
* * | ||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * | ||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * | ||
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * | ||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * | ||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * | ||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * | ||
* POSSIBILITY OF SUCH DAMAGE. * | ||
* * | ||
***********************************************************************************************************************/ | ||
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/** | ||
@file | ||
@author Andrew D. Zonenberg | ||
@brief Base class for ARM CoreSight components (other than CPU cores) on a debug APB bus | ||
*/ | ||
#ifndef ARMCoreSightDevice_h | ||
#define ARMCoreSightDevice_h | ||
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class ARMCoreSightDevice : public ARMAPBDevice | ||
{ | ||
public: | ||
ARMCoreSightDevice( | ||
ARMDebugMemAccessPort* ap, uint32_t address, ARMDebugPeripheralIDRegisterBits idreg); | ||
virtual ~ARMCoreSightDevice(); | ||
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virtual std::string GetDescription(); | ||
virtual void PrintInfo(); | ||
}; | ||
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#endif |
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