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Active Probe Host Prototype #4

merged 9 commits into from Jan 10, 2021


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I've finished the schematic. I'll let it stew in my brain for a few days then come back and work on the layout, and eventually start writing some gateware.

Feel free to suggest improvements to the power architecture, this was just the simplest, cheapest method I thought of. I'm using RC networks of values I already have in the design to sequence the power supplies. This may be a bad idea but I'm not aware of a specific reason why.

Also this is my first time doing anything with a 7-series FPGA, so I am very likely to have missed something there.

@davidlenfesty davidlenfesty marked this pull request as ready for review January 8, 2021 20:42
@azonenberg azonenberg merged commit 47fe316 into azonenberg:master Jan 10, 2021
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2 participants