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azya52 edited this page Feb 13, 2023 · 22 revisions

CPU

General Purpose Registers

The internal RAM is organized as 128 x 4-bit general purpose registers, divided into four banks B0..B3, each of which contains 4 pages of 8 nibbles:

Bank 0

Page 0: R0 .. R7
Page 1: R8 .. R15
Page 2: R16 .. R23
Page 3: R24 .. R31

Bank 1

Page 0: R0 .. R7
Page 1: R8 .. R15
Page 2: R16 .. R23
Page 3: R24 .. R31

Bank 2

Page 0: R0 .. R7
Page 1: R8 .. R15
Page 2: R16 .. R23
Page 3: R24 .. R31

Bank 3

Page 0: R0 .. R7
Page 1: R8 .. R15
Page 2: R16 .. R23
Page 3: R24 .. R31

Instructions can use any of the 32 nibbles of the current bank of the main register set, as a source, destination, or both.
Up to 8 adjacent registers within the same page can be combined to handle up to 32-bit data. The little-endian order is used.

Special Function Registers

There a 16 x 4-bit registers. Writing to these registers does not always correspond to their contents, therefore different descriptions for reading and writing are given.

SR0

Event flags.

READ:

  • SR0.0 — Timer0 event flag
  • SR0.1 — Timer1 event flag
  • SR0.2 — Buttons event flag
  • SR0.3 — Inductive serial port (ISP) event flag

WRITE:

  • No effect

SR1

ISP flags.

READ:

  • SR1.0 — ISP receive flag, through buffer registers (even if with an error)
  • SR1.1 — ISP receive flag, through DMA (SA)
  • SR1.2 — ISP transmit flag, through buffer registers
  • SR1.3 — ISP transmit flag, through DMA (SA)

WRITE:

  • Any value clears SR1 and SR0.3

SR2

Some flags associated with ISP.

READ:

  • SR2.0 — ISP receive error
  • SR2.1 — ?
  • SR2.2 — ?
  • SR2.3 — ?

WRITE:

  • Any value clears SR2

SR3

READ:
Number (0-3) of timer1 overflows since previous read SR3 (?)

WRITE:
ISP control.

  • SR3.0
    0: Transmit/receive through ISP buffer registers
    1: Transmit/receive from/to SRAM through (SA) (Number of transmitted bytes = 256 - SA % 256)
  • SR3.1
    0: Transmitter disable
    1: Transmitter enable
  • SR3.2 — ?
  • SR3.3 — ?

SR4

READ:
Number (0-3) of timer0 overflows since previous read SR4 (?)

WRITE:
ISP control.

  • SR4.0
    1: Start ISP transmitting
  • SR4.1
    1: ? Receiver enable
  • SR4.2 — ?
  • SR4.3 — ?

SR5

ISP buffers, high nibble.

READ:
ISP receive data buffer

  • Get received/transmitted data (if SR4.1 = 1)

WRITE:
ISP transmit data buffer

  • Loads data to be transmitted

SR6

ISP buffers, low nibble.

READ:
ISP receive data buffer

  • Get received/transmitted data (if SR4.1 = 1)

WRITE:
ISP transmit data buffer

  • Loads data to be transmitted

SR7

Button press flags.

READ:

  • SR7.0 — LEFT
  • SR7.1 — RIGHT
  • SR7.2 — TRANSMIT
  • SR7.3 — MODE

WRITE:

  • Any value clears SR7 and SR0.2

SR8

Button pressed flags.

READ:

  • SR8.0 — 1 while LEFT is pressed
  • SR8.1 — 1 while RIGHT is pressed
  • SR8.2 — 1 while TRANSMIT is pressed
  • SR8.3 — 1 while MODE is pressed

WRITE:

  • No effect

SR9

Timer1 flags.

READ:

  • SR9.0 — Timer1 stopwatch clear flag (LEFT is pressed while the stopwatch is stopped)
  • SR9.1 — Timer1 stopwatch split flag (LEFT is pressed while the stopwatch is running)
  • SR9.2 — Timer1 overflow flag
  • SR9.3 — Timer1 stopwatch running flag (RIGHT is pressed)

WRITE:

  • SR9.0
    1: Clear SR9.0, if after that SR9 == 0 clear SR0.1
  • SR9.1
    1: Clear SR9.1, if after that SR9 == 0 clear SR0.1
  • SR9.2
    1: Clear SR9.2, if after that SR9 == 0 clear SR0.1
  • SR9.3
    1: Clear SR9.3, if after that SR9 == 0 clear SR0.1

SR10

Timer1 value and control.

READ:

  • Timer1 1/100 sec. BCD

WRITE:

  • SR10.0
    1: Timer1 Stopwatch special mode
  • SR10.1
    1: Timer1 reset (SR10 ← 0) (cancels Stopwatch mode)
  • SR10.2
    1: Timer1 stop (cancels Stopwatch mode)
  • SR10.3
    1: Timer1 start (cancels Stopwatch mode)

SR11

Timer1 split value (when the LEFT is pressed while the stopwatch is running SR11 ← SR10).

READ:

  • Split value.

WRITE:

  • No effect.

SR12

Timer0 flags.

READ:

  • SR12.0 — Timer0 overflow flag
  • SR12.1 — Set every 1/4 sec.
  • SR12.2 — Set every 1/16 sec.
  • SR12.3 — Set every 1/32 sec.

WRITE:

  • SR12.0
    1: Clear SR12.0, if after that SR12 == 0 clear SR0.0
  • SR12.1
    1: Clear SR12.1, if after that SR12 == 0 clear SR0.0
  • SR12.2
    1: Clear SR12.2, if after that SR12 == 0 clear SR0.0
  • SR12.3
    1: Clear SR12.3, if after that SR12 == 0 clear SR0.0

SR13

Timer0 control.

READ:

  • SR13.0 — Timer0 overflow disabled
  • SR13.1 — Timer0 1/4 sec. disabled
  • SR13.2 — Timer0 1/16 sec. disabled
  • SR13.3 — Timer0 1/32 sec. disabled

WRITE:

  • SR13.0
    1: Disable Timer0 overflow
  • SR13.1
    1: Disable Timer0 1/4 sec.
  • SR13.2
    1: Disable Timer0 1/16 sec.
  • SR13.3
    1: Disable Timer0 1/32 sec. interrupt

SR14

Timer0 value.

READ: Timer0 1/16 sec.

WRITE: Any value clears Timer0

SR15

READ:

  • SR15.0 — ? (always 0)
  • SR15.1 — ? (always 0)
  • SR15.2 — ? (always 0)
  • SR15.3 — Set while erasing

WRITE:

  • SR15.0
    1: 1-short beep
  • SR15.1
    1: Beep tone generator disable
  • SR15.2
    1: Beep tone generator enable (4096Hz)
  • SR15.3
    1: Erase SRAM starting with SA. After erasing SA = 0.

Stack

The stack consists of three 12-bit registers.

Instruction Execution Time

The CPU is clocked at 32768Hz. All instructions, except for multi-nibbles, are executed in 8 clock cycles.
For multi-nibbles instructions, the execution time increases in multiples of the number of processed nibbles.

Example:

	ADD RA0, RA1 ;8 cycles, 244.14us
	ADDM RA0, RB7 ;64 cycles, 1953.13us

LCD Controller

Display Data RAM

8 bit wide RAM occupy addresses 0x0 - 0x39. Stores display data represented in 8-bit character codes

Display Attribute RAM

1 bit wide RAM occupy addresses 0x40 - 0x67. Stores the blink attribute (0x1: on, 0x0: off) for the corresponding character in DDRAM

Control Registers

Control registers occupy addresses 0x70 - 0x7F.

0x70

Display Сonfiguration (top half), 2 bit.

  • 0: normal
  • 1: horizontal reflection
  • 2: horizontal and vertical reflection
  • 3: horizontal and vertical reflection

0x71

Display Сonfiguration (bottom half), 2 bit.

  • 0: horizontal and vertical reflection
  • 1: vertical reflection
  • 2: normal
  • 3: normal

0x72

?

0x73

?

0x74

Display Refresh Control, 1 bit.

  • 0: enable
  • 1: disable

0x75

Blink Mode, 1 bit.

  • 0: Blink to white
  • 1: Blink to black

0x76

Display Test, 1 bit.

  • 0: Normal mode
  • 1: Test Mode (full screen 0xFF)

0x77

Draw Mode, 1 bit.

  • 0: Char mode
  • 1: Direct mode

0x78

Auto Display Refresh Control, 1 bit.

  • 0: Disable
  • 1: Enable (4 FPS)

0x79

Contrast increase, any value.

0x7A

Сontrast decrease, any value.

0x7B

Clear control registers, any value.

0x7C

Force display refresh after the current one ends (Reset scanning pointer after reaching 512), any value.

0x7D

Clear display, any value.

0x7E

Clear blink attributes, any value.

0x7F

Force display refresh (Reset scanning pointer immediately), any value.

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