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Redesign and continuation of the FPGC5 but with a pipelined CPU (with hazard detection, branch prediction, etc.), memory cache (L1 and L2), and a better architecture for running BCC code

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b4rt-dev/FPGC6

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Redesign and continuation of the FPGC5 but with a pipelined CPU (with hazard detection, branch prediction, etc.), memory cache (L1 and L2), and a better architecture for running BCC code

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