{"payload":{"header_redesign_enabled":false,"results":[{"id":"54040649","archived":false,"color":"#b07219","followers":12,"has_funding_file":false,"hl_name":"balanx/fizzim2","hl_trunc_description":"FSM (Finite State Machine) tools for Verilog HDL.","language":"Java","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":54040649,"name":"fizzim2","owner_id":3511246,"owner_login":"balanx","updated_at":"2022-12-19T14:11:39.225Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":79,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Abalanx%252Ffizzim2%2B%2Blanguage%253AJava","metadata":null,"csrf_tokens":{"/balanx/fizzim2/star":{"post":"T45_sy1kN8IrkGrdI7t-IzGaPyS9d_Tu0zOjYe_HCO-mCBKw5yZYYjKeRRDhBq7X3gdS5wV-7pUhFIyuaCJmBA"},"/balanx/fizzim2/unstar":{"post":"7_JayGAKEK_9eAQ6c0mZt0Ni3zQHkQNKm0GosA0fEj3nO1dlR1Yp5-Yp7ZJh_SCIyzUYYWlWnOsB5Pe-nvVA6A"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"TIaWyWsPiLsBS4q3YeyO2YOebQnHosGiG-5YF-Q-jW2Rl6yBwaodjmIxHYsyDprNkV2o-KFs46BY1Ogt8LX5Qw"}}},"title":"Repository search results"}