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usrp_e : Modify overo board file to setup hardware for usrp_e driver.

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1 parent c3396d4 commit 4f6c8fa3a33ba374ce1f8f3e83ebae2bcc505962 Philip Balister committed May 11, 2011
Showing with 179 additions and 2 deletions.
  1. +179 −2 arch/arm/mach-omap2/board-overo.c
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181 arch/arm/mach-omap2/board-overo.c
@@ -36,6 +36,8 @@
#include <linux/mtd/partitions.h>
#include <linux/mmc/host.h>
+#include <linux/spi/spi.h>
+
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
@@ -196,7 +198,9 @@ static struct platform_device overo_smsc911x2_device = {
static struct platform_device *smsc911x_devices[] = {
&overo_smsc911x_device,
+#if 0
&overo_smsc911x2_device,
+#endif
};
static inline void __init overo_init_smsc911x(void)
@@ -226,6 +230,7 @@ static inline void __init overo_init_smsc911x(void)
/* set up second smsc911x chip */
+#if 0
if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) {
printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n");
return;
@@ -245,6 +250,7 @@ static inline void __init overo_init_smsc911x(void)
overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO);
overo_smsc911x2_resources[1].end = 0;
+#endif
platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices));
}
@@ -391,6 +397,24 @@ static struct regulator_consumer_supply overo_vdda_dac_supply =
static struct regulator_consumer_supply overo_vdds_dsi_supply =
REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+#if 0 // Delete all this code when SPIDEV works
+
+struct flash_partitions {
+ struct mtd_partition *parts;
+ int nr_parts;
+};
+
+static struct spi_board_info overo_mcspi_board_info[] = {
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 12000000, // 12 MHz
+ .bus_num = 1,
+ .chip_select = 0,
+ .mode = SPI_MODE_1,
+ },
+};
+#endif
+
static struct mtd_partition overo_nand_partitions[] = {
{
.name = "xloader",
@@ -470,8 +494,7 @@ static struct omap2_hsmmc_info mmc[] = {
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
- .gpio_wp = -EINVAL,
- .transceiver = true,
+ .gpio_wp = 150,
.ocr_mask = 0x00100000, /* 3.3V */
},
{} /* Terminator */
@@ -485,6 +508,7 @@ static struct regulator_consumer_supply overo_vmmc1_supply = {
#include <linux/leds.h>
static struct gpio_led gpio_leds[] = {
+#if 0 /* These are used by the e100 */
{
.name = "overo:red:gpio21",
.default_trigger = "heartbeat",
@@ -497,6 +521,7 @@ static struct gpio_led gpio_leds[] = {
.gpio = 22,
.active_low = true,
},
+#endif
{
.name = "overo:blue:COM",
.default_trigger = "mmc0",
@@ -771,6 +796,154 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
+static void __init usrp1_e_init(void)
+{
+ unsigned int tmp;
+
+ printk("Setup up gpmc timing.\n");
+
+// Set up CS4, data read/write
+
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG7, 0x0);
+ udelay(100);
+
+#if 1
+ // Signal control parameters per chip select
+ tmp = gpmc_cs_read_reg(4, GPMC_CS_CONFIG1);
+// tmp |= (GPMC_CONFIG1_MUXADDDATA);
+// tmp |= (GPMC_CONFIG1_WRITETYPE_SYNC);
+// tmp |= (GPMC_CONFIG1_READTYPE_SYNC);
+ tmp |= (GPMC_CONFIG1_FCLK_DIV(0));
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG1, tmp);
+ printk("GPMC_CONFIG1 reg: %x\n", tmp);
+#endif
+
+#if 1
+ // CS signal timing parameter configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG2_CSONTIME(1); /* 1 */
+ tmp |= GPMC_CONFIG2_CSWROFFTIME(16); /* 16 */
+ tmp |= GPMC_CONFIG2_CSRDOFFTIME(16); /* 16 */
+ printk("GPMC_CONFIG2 reg: %x\n", tmp);
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG2, tmp);
+#endif
+
+#if 1
+ // nADV signal timing parameter configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG3_ADVONTIME(1);
+ tmp |= GPMC_CONFIG3_ADVRDOFFTIME(2);
+ tmp |= GPMC_CONFIG3_ADVWROFFTIME(2);
+ printk("GPMC_CONFIG3 reg: %x\n", tmp);
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG3, tmp);
+#endif
+
+#if 1
+ // nWE and nOE signals timing parameter configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG4_WEONTIME(3); /* 3 */
+ tmp |= GPMC_CONFIG4_WEOFFTIME(16); /* 16 */
+ tmp |= GPMC_CONFIG4_OEONTIME(3); /* 3 */
+ tmp |= GPMC_CONFIG4_OEOFFTIME(16); /* 16 */
+ printk("GPMC_CONFIG4 reg: %x\n", tmp);
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG4, tmp);
+#endif
+
+#if 1
+ // RdAccess time and Cycle time timing parameters configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG5_PAGEBURSTACCESSTIME(1);
+ tmp |= GPMC_CONFIG5_RDACCESSTIME(15); /* 15 */
+ tmp |= GPMC_CONFIG5_WRCYCLETIME(17); /* 17 */
+ tmp |= GPMC_CONFIG5_RDCYCLETIME(17); /* 17 */
+ printk("GPMC_CONFIG5 reg: %x\n", tmp);
+
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG5, tmp);
+#endif
+
+#if 1
+ // WrAccessTime WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround params
+ tmp = (1<<31);
+ tmp |= GPMC_CONFIG6_WRACCESSTIME(15); /* 15 */
+ tmp |= GPMC_CONFIG6_WRDATAONADMUXBUS(3);
+ tmp |= GPMC_CONFIG6_CYCLE2CYCLEDELAY(0);
+ tmp |= GPMC_CONFIG6_BUSTURNAROUND(0);
+ printk("GPMC_CONFIG6 reg: %x\n", tmp);
+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG6, tmp);
+#endif
+
+// Configure timing for CS6, wishbone access
+
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG7, 0x0);
+ udelay(100);
+
+#if 1
+ // Signal control parameters per chip select
+ tmp = gpmc_cs_read_reg(6, GPMC_CS_CONFIG1);
+// tmp |= (GPMC_CONFIG1_MUXADDDATA);
+// tmp |= (GPMC_CONFIG1_WRITETYPE_SYNC);
+// tmp |= (GPMC_CONFIG1_READTYPE_SYNC);
+ tmp |= (GPMC_CONFIG1_FCLK_DIV(0));
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG1, tmp);
+ printk("GPMC_CONFIG1 reg: %x\n", tmp);
+#endif
+
+#if 1
+ // CS signal timing parameter configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG2_CSONTIME(1);
+ tmp |= GPMC_CONFIG2_CSWROFFTIME(20);
+ tmp |= GPMC_CONFIG2_CSRDOFFTIME(20);
+ printk("GPMC_CONFIG2 reg: %x\n", tmp);
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG2, tmp);
+#endif
+
+#if 1
+ // nADV signal timing parameter configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG3_ADVONTIME(1);
+ tmp |= GPMC_CONFIG3_ADVRDOFFTIME(2);
+ tmp |= GPMC_CONFIG3_ADVWROFFTIME(2);
+ printk("GPMC_CONFIG3 reg: %x\n", tmp);
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG3, tmp);
+#endif
+
+#if 1
+ // nWE and nOE signals timing parameter configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG4_WEONTIME(3);
+ tmp |= GPMC_CONFIG4_WEOFFTIME(18);
+ tmp |= GPMC_CONFIG4_OEONTIME(3);
+ tmp |= GPMC_CONFIG4_OEOFFTIME(18);
+ printk("GPMC_CONFIG4 reg: %x\n", tmp);
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG4, tmp);
+#endif
+
+#if 1
+ // RdAccess time and Cycle time timing paraters configuration
+ tmp = 0;
+ tmp |= GPMC_CONFIG5_PAGEBURSTACCESSTIME(1);
+ tmp |= GPMC_CONFIG5_RDACCESSTIME(18);
+ tmp |= GPMC_CONFIG5_WRCYCLETIME(21);
+ tmp |= GPMC_CONFIG5_RDCYCLETIME(21);
+ printk("GPMC_CONFIG5 reg: %x\n", tmp);
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG5, tmp);
+#endif
+
+#if 1
+ // WrAccessTime WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround params
+ tmp = 0;
+ tmp |= GPMC_CONFIG6_WRACCESSTIME(15);
+ tmp |= GPMC_CONFIG6_WRDATAONADMUXBUS(3);
+ tmp |= GPMC_CONFIG6_CYCLE2CYCLEDELAY(3);
+ tmp |= GPMC_CONFIG6_CYCLE2CYCLESAMECSEN;
+ tmp |= GPMC_CONFIG6_BUSTURNAROUND(0);
+ printk("GPMC_CONFIG6 reg: %x\n", tmp);
+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG6, tmp);
+#endif
+
+}
+
static void __init overo_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -782,10 +955,14 @@ static void __init overo_init(void)
usb_ehci_init(&ehci_pdata);
overo_spi_init();
overo_init_smsc911x();
+#if 0 /* No LCD for E100 */
overo_display_init();
+#endif
overo_init_led();
overo_init_keys();
+ usrp1_e_init();
+
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);

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