diff --git a/Makefile b/Makefile
index 484c2b4af..374be13c2 100644
--- a/Makefile
+++ b/Makefile
@@ -11,7 +11,28 @@ define current_directory
 $(realpath $(dir $(lastword $(MAKEFILE_LIST))))
 endef
 
+# Check cross compiler
+ifneq ($(findstring clang,$(CROSS_COMPILE)),)
+CC_IS_CLANG =	y
+else
+CC_IS_GCC =	y
+endif
+
 # Setup toolchain macros
+
+ifdef CC_IS_CLANG
+clang_version:=$(strip $(patsubst clang%, %, $(notdir $(CROSS_COMPILE))))
+clang_path:=$(dir $(wildcard $(abspath $(CROSS_COMPILE))))
+cpp=		$(clang_path)clang-cpp$(clang_version)
+sstrip= 	$(clang_path)llvm-strip$(clang_version)
+cc=			$(clang_path)clang$(clang_version)
+ld = 		$(clang_path)ld.lld$(clang_version)
+as=			$(clang_path)llvm-as$(clang_version)
+objcopy=	$(clang_path)llvm-objcopy$(clang_version)
+objdump=	$(clang_path)llvm-objdump$(clang_version)
+readelf=	$(clang_path)llvm-readelf$(clang_version)
+size=		$(clang_path)llvm-size$(clang_version)
+else
 cpp=		$(CROSS_COMPILE)cpp
 sstrip= 	$(CROSS_COMPILE)strip
 cc=			$(CROSS_COMPILE)gcc
@@ -21,6 +42,7 @@ objcopy=	$(CROSS_COMPILE)objcopy
 objdump=	$(CROSS_COMPILE)objdump
 readelf=	$(CROSS_COMPILE)readelf
 size=		$(CROSS_COMPILE)size
+endif
 
 HOST_CC:=gcc
 
@@ -174,36 +196,57 @@ objs-y+=$(config_obj)
 
 build_macros:=
 ifeq ($(arch_mem_prot),mmu)
-build_macros+=-DMEM_PROT_MMU
+	build_macros+=-DMEM_PROT_MMU
 endif
 ifeq ($(arch_mem_prot),mpu)
-build_macros+=-DMEM_PROT_MPU
+	build_macros+=-DMEM_PROT_MPU
+endif
+
+ifeq ($(CC_IS_GCC),y)
+	build_macros+=-DCC_IS_GCC
+else ifeq ($(CC_IS_CLANG),y)
+	build_macros+=-DCC_IS_CLANG
 endif
 
 override CPPFLAGS+=$(addprefix -I, $(inc_dirs)) $(arch-cppflags) \
 	$(platform-cppflags) $(build_macros)
 vpath:.=CPPFLAGS
 
+HOST_CPPFLAGS+=$(addprefix -I, $(inc_dirs)) $(arch-cppflags) \
+	$(platform-cppflags) $(build_macros)
+
 ifeq ($(DEBUG), y)
 	debug_flags:=-g
 	OPTIMIZATIONS:=g
 endif
 
-cflags_warns:= \
-	-Warith-conversion -Wbuiltin-declaration-mismatch \
-	-Wcomments  -Wdiscarded-qualifiers \
-	-Wimplicit-fallthrough \
-	-Wswitch-unreachable -Wreturn-local-addr  \
-	-Wshift-count-negative  -Wuninitialized \
-	-Wunused -Wunused-local-typedefs  -Wunused-parameter \
-	-Wunused-result -Wvla \
-	-Wconversion -Wsign-conversion \
-	-Wmissing-prototypes -Wmissing-declarations  \
-	-Wswitch-default -Wshadow -Wshadow=global \
-	-Wcast-qual -Wunused-macros
+
+ifeq ($(CC_IS_GCC),y)
+	cflags_warns:= \
+		-Warith-conversion -Wbuiltin-declaration-mismatch \
+		-Wcomments  -Wdiscarded-qualifiers \
+		-Wimplicit-fallthrough \
+		-Wswitch-unreachable -Wreturn-local-addr  \
+		-Wshift-count-negative  -Wuninitialized \
+		-Wunused -Wunused-local-typedefs  -Wunused-parameter \
+		-Wunused-result -Wvla \
+		-Wconversion -Wsign-conversion \
+		-Wmissing-prototypes -Wmissing-declarations  \
+		-Wswitch-default -Wshadow -Wshadow=global \
+		-Wcast-qual -Wunused-macros \
+		-Wstrict-prototypes -Wunused-but-set-variable
+
+	override CFLAGS+=-Wno-unused-command-line-argument \
+		-pedantic -pedantic-errors
+	override LDFLAGS+=--no-check-sections
+else ifeq ($(CC_IS_CLANG), y)
+	override CFLAGS+=-Wno-unused-command-line-argument --target=$(clang_arch_target)
+	override CPPFLAGS+=--target=$(clang_arch_target) -ffreestanding
+	override LDFLAGS+=--no-check-sections
+endif
 
 override CFLAGS+=-O$(OPTIMIZATIONS) -Wall -Werror -Wextra $(cflags_warns) \
-	-ffreestanding -std=c11 -pedantic -pedantic-errors -fno-pic \
+	-ffreestanding -std=c11 -fno-pic \
 	$(arch-cflags) $(platform-cflags) $(CPPFLAGS) $(debug_flags)
 
 override ASFLAGS+=$(CFLAGS) $(arch-asflags) $(platform-asflags)
@@ -231,7 +274,7 @@ endif
 
 $(ld_script_temp):
 	@echo "Pre-processing		$(patsubst $(cur_dir)/%, %, $(ld_script))"
-	@$(cc) -E $(addprefix -I, $(inc_dirs)) -x assembler-with-cpp  $(CPPFLAGS) \
+	@$(cc) $(CFLAGS) -E $(addprefix -I, $(inc_dirs)) -x assembler-with-cpp  $(CPPFLAGS) \
 		$(ld_script) | grep -v '^\#' > $(ld_script_temp)
 
 ifneq ($(build_targets),)
@@ -245,7 +288,7 @@ $(ld_script_temp).d: $(ld_script)
 
 $(build_dir)/%.d : $(src_dir)/%.[c,S]
 	@echo "Creating dependency	$(patsubst $(cur_dir)/%, %, $<)"
-	@$(cc) -MM -MG -MT "$(patsubst %.d, %.o, $@) $@"  $(CPPFLAGS) $< > $@
+	@$(cc) $(CFLAGS) -MM -MG -MT "$(patsubst %.d, %.o, $@) $@"  $(CPPFLAGS) $< > $@
 
 $(objs-y):
 	@echo "Compiling source	$(patsubst $(cur_dir)/%, %, $<)"
@@ -264,7 +307,7 @@ ifneq ($(wildcard $(asm_defs_src)),)
 $(asm_defs_hdr): $(asm_defs_src)
 	@echo "Generating header	$(patsubst $(cur_dir)/%, %, $@)"
 	@$(cc) -S $(CFLAGS) -DGENERATING_DEFS $< -o - \
-		| awk '($$1 == "->") \
+		| awk '($$1 == "//#" || $$1 == "##" || $$1 == "@#")   \
 			{ gsub("#", "", $$3); print "#define " $$2 " " $$3 }' > $@
 
 $(asm_defs_hdr).d: $(asm_defs_src)
@@ -276,13 +319,13 @@ endif
 $(config_dep): $(config_src)
 	@echo "Creating dependency	$(patsubst $(cur_dir)/%, %,\
 		 $(patsubst %.d,%, $@))"
-	@$(cc) -MM -MG -MT "$(config_obj) $@" $(CPPFLAGS) $(filter %.c, $^) > $@
-	@$(cc) $(CPPFLAGS) -S $(config_src) -o - | grep ".incbin" | \
+	@$(cc) $(CFLAGS) -MM -MG -MT "$(config_obj) $@" $(CPPFLAGS) $(filter %.c, $^) > $@
+	@$(cc) $(CFLAGS) $(CPPFLAGS) -S $(config_src) -o - | grep ".incbin" | \
 		awk '{ gsub("\"", "", $$2); print "$(config_obj): " $$2 }' >> $@
 
 $(config_def_generator): $(config_def_generator_src) $(config_src)
 	@echo "Compiling generator	$(patsubst $(cur_dir)/%, %, $@)"
-	@$(HOST_CC) $^ $(build_macros) $(CPPFLAGS) -DGENERATING_DEFS \
+	@$(HOST_CC) $^ $(build_macros) $(HOST_CPPFLAGS) -DGENERATING_DEFS \
 		$(addprefix -I, $(inc_dirs)) -o $@
 
 $(config_defs): $(config_def_generator)
@@ -291,7 +334,7 @@ $(config_defs): $(config_def_generator)
 
 $(platform_def_generator): $(platform_def_generator_src) $(platform_description)
 	@echo "Compiling generator	$(patsubst $(cur_dir)/%, %, $@)"
-	@$(HOST_CC) $^ $(build_macros) $(CPPFLAGS) -DGENERATING_DEFS -D$(ARCH) \
+	@$(HOST_CC) $^ $(build_macros) $(HOST_CPPFLAGS) -DGENERATING_DEFS -D$(ARCH) \
 		$(addprefix -I, $(inc_dirs)) -o $@
 
 $(platform_defs): $(platform_def_generator)
diff --git a/src/arch/armv8/aarch32/arch_sub.mk b/src/arch/armv8/aarch32/arch_sub.mk
index 7cba82007..5765c5afa 100644
--- a/src/arch/armv8/aarch32/arch_sub.mk
+++ b/src/arch/armv8/aarch32/arch_sub.mk
@@ -4,6 +4,8 @@
 CROSS_COMPILE ?= arm-none-eabi-
 
 arch-cppflags+=-DAARCH32
-arch-cflags+=
+arch-cflags+= -mfloat-abi=soft
 arch-asflags+=
 arch-ldflags+=
+
+clang_arch_target:=arm
diff --git a/src/arch/armv8/aarch32/boot.S b/src/arch/armv8/aarch32/boot.S
index 0b613c225..8e56eedfe 100644
--- a/src/arch/armv8/aarch32/boot.S
+++ b/src/arch/armv8/aarch32/boot.S
@@ -184,7 +184,6 @@ _set_master_cpu:
 /*****  Helper functions for boot code. ******/
 
 .global boot_clear
-.func boot_clear
 boot_clear:
 2:
     mov r8, #0
@@ -195,7 +194,6 @@ boot_clear:
 	b 2b
 1:
 	bx lr
-.endfunc
 
 /*
  * Code adapted from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0"
@@ -203,7 +201,6 @@ boot_clear:
  * r0 - cache level to be invalidated (0 - dl1$, 1 - il1$)
  */
 .global boot_cache_invalidate
-.func boot_cache_invalidate
 boot_cache_invalidate:
     mcr p15, 2, r0, c0, c0, 0 // write CSSELR (cache size selection)
     mrc p15, 1, r4, c0, c0, 0 // read CCSIDR (cache size id)
@@ -230,5 +227,4 @@ set_loop:
     cmp r5, r3 // last way reached yet?
     ble way_loop // if not, iterate way_loop
     bx lr
-.endfunc
 
diff --git a/src/arch/armv8/aarch32/inc/arch/spinlock.h b/src/arch/armv8/aarch32/inc/arch/spinlock.h
index e891b6184..4893e6b6e 100644
--- a/src/arch/armv8/aarch32/inc/arch/spinlock.h
+++ b/src/arch/armv8/aarch32/inc/arch/spinlock.h
@@ -36,15 +36,15 @@ static inline void spin_lock(spinlock_t* lock)
     __asm__ volatile(
         /* Get ticket */
         "1:\n\t"
-        "ldaex  %r0, %3\n\t"
-        "add    %r1, %r0, #1\n\t"
-        "strex  %r2, %r1, %3\n\t"
-        "cmp  %r2, #0\n\t"
+        "ldaex  %0, %3\n\t"
+        "add    %1, %0, #1\n\t"
+        "strex  %2, %1, %3\n\t"
+        "cmp  %2, #0\n\t"
         "bne 1b \n\t"
         /* Wait for your turn */
         "2:\n\t"
-        "ldr    %r1, %4\n\t"
-        "cmp    %r0, %r1\n\t"
+        "ldr    %1, %4\n\t"
+        "cmp    %0, %1\n\t"
         "beq   3f\n\t"
         "wfe \n\t"
         "b 2b\n\t"
@@ -58,9 +58,9 @@ static inline void spin_unlock(spinlock_t* lock)
 
     __asm__ volatile(
         /* increment to next ticket */
-        "ldr    %r0, %1\n\t"
-        "add    %r0, %r0, #1\n\t"
-        "stl    %r0, %1\n\t"
+        "ldr    %0, %1\n\t"
+        "add    %0, %0, #1\n\t"
+        "stl    %0, %1\n\t"
         "dsb ish\n\t"
         "sev\n\t" : "=&r"(temp) : "Q"(lock->next) : "memory");
 }
diff --git a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
index aac8e17bc..d35c59d9d 100644
--- a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
+++ b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
@@ -11,7 +11,7 @@
 #ifndef __ASSEMBLER__
 
 #define SYSREG_GEN_ACCESSORS(name, op1, crn, crm, op2)                                            \
-    static inline unsigned long sysreg_##name##_read()                                            \
+    static inline unsigned long sysreg_##name##_read(void)                                        \
     {                                                                                             \
         unsigned long _temp;                                                                      \
         __asm__ volatile("mrc p15, " #op1 ", %0, " #crn ", " #crm ", %1\n\r" : "=r"(_temp)        \
@@ -24,7 +24,7 @@
     }
 
 #define SYSREG_GEN_ACCESSORS_BANKED(name, reg)                       \
-    static inline unsigned long sysreg_##name##_read()               \
+    static inline unsigned long sysreg_##name##_read(void)           \
     {                                                                \
         unsigned long _temp;                                         \
         __asm__ volatile("mrs %0, " XSTR(reg) "\n\r" : "=r"(_temp)); \
@@ -36,7 +36,7 @@
     }
 
 #define SYSREG_GEN_ACCESSORS_64(reg, op1, crm)                                                    \
-    static inline unsigned long long sysreg_##reg##_read()                                        \
+    static inline unsigned long long sysreg_##reg##_read(void)                                    \
     {                                                                                             \
         unsigned long long _temp, _tempH;                                                         \
         __asm__ volatile("mrrc p15, " #op1 ", %0, %1, " #crm "\n\r" : "=r"(_temp), "=r"(_tempH)); \
@@ -49,7 +49,7 @@
     }
 
 #define SYSREG_GEN_ACCESSORS_MERGE(reg, reg1, reg2)                                         \
-    static inline unsigned long long sysreg_##reg##_read()                                  \
+    static inline unsigned long long sysreg_##reg##_read(void)                              \
     {                                                                                       \
         return ((unsigned long long)sysreg_##reg2##_read() << 32) | sysreg_##reg1##_read(); \
     }                                                                                       \
@@ -155,12 +155,12 @@ static inline void arm_at_s12e1w(vaddr_t vaddr)
     __asm__ volatile("mcr p15, 0, %0, c7, c8, 5" ::"r"(vaddr)); // ats12nsopw
 }
 
-static inline void arm_tlbi_alle2is()
+static inline void arm_tlbi_alle2is(void)
 {
     __asm__ volatile("mcr p15, 4, r0, c8, c7, 0");
 }
 
-static inline void arm_tlbi_vmalls12e1is()
+static inline void arm_tlbi_vmalls12e1is(void)
 {
     __asm__ volatile("mcr p15, 0, r0, c8, c7, 0");
 }
diff --git a/src/arch/armv8/aarch64/arch_sub.mk b/src/arch/armv8/aarch64/arch_sub.mk
index 8d42116eb..f41c222e1 100644
--- a/src/arch/armv8/aarch64/arch_sub.mk
+++ b/src/arch/armv8/aarch64/arch_sub.mk
@@ -7,3 +7,5 @@ arch-cppflags+=-DAARCH64
 arch-cflags+= -mcmodel=large -mstrict-align
 arch-asflags+=
 arch-ldflags+=
+
+clang_arch_target:=aarch64
diff --git a/src/arch/armv8/aarch64/boot.S b/src/arch/armv8/aarch64/boot.S
index 5c2a159ca..a90d1f655 100644
--- a/src/arch/armv8/aarch64/boot.S
+++ b/src/arch/armv8/aarch64/boot.S
@@ -62,7 +62,7 @@ _reset_handler:
 	 * this early in the initialization.
 	 */
 
-	mov x3, x0, lsr #8
+	lsr x3, x0, #8
 	and x3, x3, 0xff
 	adr x4, platform
 	ldr x4, [x4, PLAT_ARCH_OFF+PLAT_ARCH_CLUSTERS_OFF+PLAT_CLUSTERS_CORES_NUM_OFF]
@@ -180,7 +180,6 @@ _set_master_cpu:
 /***** 	Helper functions for boot code. ******/
 
 .global boot_clear
-.func boot_clear
 boot_clear:
 2:
 	cmp	x16, x17
@@ -189,7 +188,6 @@ boot_clear:
 	b	2b
 1:
 	ret
-.endfunc
 
 /*
  * Code taken from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0"
@@ -197,7 +195,6 @@ boot_clear:
  * x0 - cache level to be invalidated (0 - dl1$, 1 - il1$, 2 - l2$)
  */
 .global boot_cache_invalidate
-.func boot_cache_invalidate
 boot_cache_invalidate:
 	msr csselr_el1, x0
 	mrs x4, ccsidr_el1 // read cache size id.
@@ -224,6 +221,4 @@ set_loop:
 	cmp x5, x3 // last way reached yet?
 	ble way_loop // if not, iterate way_loop
 	ret
-.endfunc
-
 
diff --git a/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h b/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h
index ba2f609e7..0dbf632cd 100644
--- a/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h
+++ b/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h
@@ -47,7 +47,7 @@
 #ifndef __ASSEMBLER__
 
 #define SYSREG_GEN_ACCESSORS_NAME(reg, name)                          \
-    static inline unsigned long sysreg##reg##read()                   \
+    static inline unsigned long sysreg##reg##read(void)               \
     {                                                                 \
         unsigned long _temp;                                          \
         __asm__ volatile("mrs %0, " XSTR(name) "\n\r" : "=r"(_temp)); \
@@ -138,12 +138,12 @@ static inline void arm_at_s12e1w(vaddr_t vaddr)
     __asm__ volatile("at s12e1w, %0" ::"r"(vaddr));
 }
 
-static inline void arm_tlbi_alle2is()
+static inline void arm_tlbi_alle2is(void)
 {
     __asm__ volatile("tlbi alle2is");
 }
 
-static inline void arm_tlbi_vmalls12e1is()
+static inline void arm_tlbi_vmalls12e1is(void)
 {
     __asm__ volatile("tlbi vmalls12e1is");
 }
diff --git a/src/arch/armv8/arch.mk b/src/arch/armv8/arch.mk
index c42158b25..9aa50a740 100644
--- a/src/arch/armv8/arch.mk
+++ b/src/arch/armv8/arch.mk
@@ -15,6 +15,8 @@ arch_profile_sub_dir:=$(arch_profile_dir)/$(ARCH_SUB)
 src_dirs+=$(arch_profile_sub_dir)
 
 arch-cppflags+=-DGIC_VERSION=$(GIC_VERSION)
+ifeq ($(CC_IS_GCC),y)
 arch-cflags+=-mgeneral-regs-only
+endif
 arch-asflags+=
 arch-ldflags+=
diff --git a/src/arch/armv8/armv8-a/aarch64/boot.S b/src/arch/armv8/armv8-a/aarch64/boot.S
index 708d6ba14..324e2cd8d 100644
--- a/src/arch/armv8/armv8-a/aarch64/boot.S
+++ b/src/arch/armv8/armv8-a/aarch64/boot.S
@@ -24,27 +24,27 @@ boot_arch_profile_init:
     ldr x18, =extra_allocated_phys_mem
 
 	/* Disable caches and MMU */
-	mrs x3, SCTLR_EL2 
-	bic x3, x3, #0x7	
-	msr SCTLR_EL2, x3 
-        
+	mrs x3, SCTLR_EL2
+	bic x3, x3, #0x7
+	msr SCTLR_EL2, x3
+
 	/* Skip initialy global page tables setup if not bsp (boot cpu) */
 	cbnz	x9, wait_for_bsp
 
-	adr	x16, _page_tables_start	
-	adr	x17, _page_tables_end	
+	adr	x16, _page_tables_start
+	adr	x17, _page_tables_end
 	add x16, x16, x18
 	add x17, x17, x18
-	bl	boot_clear		
+	bl	boot_clear
 
 	/* Set temporary flat mapping to switch to VAS. */
 
 	adr x4, root_l1_flat_pt
 	add x4, x4, x18
-	PTE_INDEX_ASM x5, x1, 1 
+	PTE_INDEX_ASM x5, x1, 1
 	add x6, x1, #(PTE_HYP_FLAGS | PTE_SUPERPAGE)
 	str x6, [x4, x5]
-	
+
 	/* Set global root mappings for hypervisor image */
 
 	adr x4, root_l1_pt
@@ -96,7 +96,7 @@ boot_arch_profile_init:
 	sev
 	b 	map_cpu
 
-wait_for_bsp:	
+wait_for_bsp:
 /* wait fot the bsp to finish up global mappings */
 	wfe
 	ldr x4, _boot_barrier
@@ -110,15 +110,15 @@ map_cpu:
 	 *    x5 -> pte index
 	 *    x6 -> phys addr
 	 *    x7 -> virt addr
-	 *    x8 -> aux 
+	 *    x8 -> aux
 	 */
 
 	/* get cpu root pt */
     adrp x3, _dmem_phys_beg
 	mov x8, #(CPU_SIZE + (PT_SIZE*PT_LVLS))
 	madd x3, x0, x8, x3
-	
-	mov	x16, x3	
+
+	mov	x16, x3
 	add	x17, x3, x8
 	bl	boot_clear
 
@@ -126,12 +126,12 @@ map_cpu:
 	add x4, x3, #CPU_SIZE
 
 	/* map original bootstrap flat mappings */
-	PTE_INDEX_ASM x5, x1, 0 
+	PTE_INDEX_ASM x5, x1, 0
 	adr x6, root_l1_flat_pt
 	add x6, x6, x18
 	add x6, x6, #(PTE_HYP_FLAGS | PTE_TABLE)
 	str x6, [x4, x5]
-	
+
 	ldr x5, =(PTE_INDEX(0, BAO_VAS_BASE)*8)
 	adr x6, root_l1_pt
 	add x6, x6, x18
@@ -174,7 +174,7 @@ setup_cpu:
 	/**
 	 * The operation is purposely commented out.  We are assuming monitor code already enabled smp
 	 * coherency.
-	 */ 
+	 */
 
 	/* setup translation configurations */
 	ldr x3, =TCR_EL2_DFLT
@@ -194,7 +194,7 @@ setup_cpu:
 	add x3, x3, #CPU_SIZE
 	msr TTBR0_EL2, x3
 
-	/**	
+	/**
 	 * TODO: set implementation defined registers such as ACTLR or AMAIR. Maybe define a macro for
 	 * this in a implementation oriented directory inside arch.
 	 */
@@ -208,11 +208,11 @@ setup_cpu:
 	/* Enable MMU and caches */
 	ldr x4, =(SCTLR_RES1 | SCTLR_M | SCTLR_C | SCTLR_I)
 	msr	SCTLR_EL2, x4
-	
+
 	tlbi	alle2
 	dsb	nsh
 	isb
-	
+
 	br  x5
 
 _enter_vas:
@@ -224,7 +224,7 @@ _enter_vas:
 	/* Remove temporary mapping - the L1 page holding it leaks */
 	ldr x4, =BAO_CPU_BASE
 	add x4, x4, #CPU_SIZE
-	PTE_INDEX_ASM x5, x1, 0 
+	PTE_INDEX_ASM x5, x1, 0
 	str xzr, [x4, x5]
 
     tlbi	alle2
@@ -237,7 +237,6 @@ _enter_vas:
     ret
 
 .global psci_boot_entry
-.func psci_boot_entry
 psci_boot_entry:
 warm_boot:
 
@@ -272,7 +271,7 @@ warm_boot:
 	/* map original bootstrap flat mappings */
 	mrs x3, TTBR0_EL2
 	adrp x1, _image_start
-	PTE_INDEX_ASM x1, x1, 0 
+	PTE_INDEX_ASM x1, x1, 0
 	add x3, x3, x1
 	dc civac, x3  //we invalidated l1$, but make sure the pte is not in l2$
 	add x5, x5, #(PTE_HYP_FLAGS | PTE_TABLE)
@@ -282,7 +281,7 @@ warm_boot:
 	ldr	x3, =_hyp_vector_table
 	msr	VBAR_EL2, x3
 
-    tlbi	alle2 
+    tlbi	alle2
 	dsb	nsh
 	isb
 
@@ -292,9 +291,9 @@ warm_boot:
 
 	dsb	nsh
 	isb
-	
+
 	ldr x5, =_enter_vas_warm
-	br  x5		
+	br  x5
 
 _enter_vas_warm:
 	/* Unmap bootstrat flat mappings */
@@ -302,7 +301,7 @@ _enter_vas_warm:
 	add x3, x4, #(CPU_STACK_OFF+CPU_STACK_SIZE)
 
 	add x4, x4, #CPU_SIZE
-	PTE_INDEX_ASM x5, x1, 0 
+	PTE_INDEX_ASM x5, x1, 0
 	str xzr, [x4, x5]
     tlbi	alle2
 	dsb	nsh
@@ -314,4 +313,3 @@ _enter_vas_warm:
 	bl	psci_wake
 	b 	.
 
-.endfunc
diff --git a/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h b/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h
index a72863646..789324524 100644
--- a/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h
+++ b/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h
@@ -13,7 +13,7 @@ struct cpu_arch_profile {
     struct psci_off_state psci_off_state;
 };
 
-static inline struct cpu* cpu()
+static inline struct cpu* cpu(void)
 {
     return (struct cpu*)BAO_CPU_BASE;
 }
diff --git a/src/arch/armv8/armv8-a/inc/arch/smmuv2.h b/src/arch/armv8/armv8-a/inc/arch/smmuv2.h
index 6f158a002..cf96bb595 100644
--- a/src/arch/armv8/armv8-a/inc/arch/smmuv2.h
+++ b/src/arch/armv8/armv8-a/inc/arch/smmuv2.h
@@ -380,10 +380,6 @@ ssize_t smmu_alloc_sme(void);
 void smmu_write_ctxbnk(size_t ctx_id, paddr_t root_pt, asid_t vm_id);
 void smmu_write_sme(size_t sme, streamid_t mask, streamid_t id, bool group);
 void smmu_write_s2c(size_t sme, size_t ctx_id);
-size_t smmu_sme_get_ctx(size_t sme);
-streamid_t smmu_sme_get_id(size_t sme);
-streamid_t smmu_sme_get_mask(size_t sme);
-bool smmu_sme_is_group(size_t sme);
 bool smmu_compatible_sme_exists(streamid_t mask, streamid_t id, size_t ctx, bool group);
 
 #endif
diff --git a/src/arch/armv8/armv8-a/inc/arch/tlb.h b/src/arch/armv8/armv8-a/inc/arch/tlb.h
index 6edd4a3ef..d6608fe8e 100644
--- a/src/arch/armv8/armv8-a/inc/arch/tlb.h
+++ b/src/arch/armv8/armv8-a/inc/arch/tlb.h
@@ -18,7 +18,7 @@ static inline void tlb_hyp_inv_va(vaddr_t va)
     ISB();
 }
 
-static inline void tlb_hyp_inv_all()
+static inline void tlb_hyp_inv_all(void)
 {
     DSB(ish);
     arm_tlbi_alle2is();
diff --git a/src/arch/armv8/armv8-a/iommu.c b/src/arch/armv8/armv8-a/iommu.c
index 5c89fdc07..f92732239 100644
--- a/src/arch/armv8/armv8-a/iommu.c
+++ b/src/arch/armv8/armv8-a/iommu.c
@@ -64,7 +64,7 @@ static bool iommu_vm_arch_add(struct vm* vm, streamid_t mask, streamid_t id)
     return true;
 }
 
-inline bool iommu_arch_vm_add_device(struct vm* vm, streamid_t id)
+bool iommu_arch_vm_add_device(struct vm* vm, streamid_t id)
 {
     return iommu_vm_arch_add(vm, 0, id);
 }
diff --git a/src/arch/armv8/armv8-a/pagetables.S b/src/arch/armv8/armv8-a/pagetables.S
index f9dd4f199..1f4b6a74f 100644
--- a/src/arch/armv8/armv8-a/pagetables.S
+++ b/src/arch/armv8/armv8-a/pagetables.S
@@ -5,7 +5,7 @@
 
 #include <arch/page_table.h>
 
-.section .glb_page_tables, "aw"
+.section .glb_page_tables, "aw", %nobits
 
 .globl root_l1_pt
 .balign PAGE_SIZE, 0
diff --git a/src/arch/armv8/armv8-a/psci.c b/src/arch/armv8/armv8-a/psci.c
index 6a378bbad..da8cf0418 100644
--- a/src/arch/armv8/armv8-a/psci.c
+++ b/src/arch/armv8/armv8-a/psci.c
@@ -36,7 +36,7 @@ static void psci_save_state(enum wakeup_reason wakeup_reason)
     gicc_save_state(&cpu()->arch.profile.psci_off_state.gicc_state);
 }
 
-static void psci_restore_state()
+static void psci_restore_state(void)
 {
     /**
      * The majority of the state is already restored in assembly routine psci_boot_entry.
@@ -45,7 +45,7 @@ static void psci_restore_state()
     gicc_restore_state(&cpu()->arch.profile.psci_off_state.gicc_state);
 }
 
-static void psci_wake_from_powerdown()
+static void psci_wake_from_powerdown(void)
 {
     if (cpu()->vcpu == NULL) {
         ERROR("cpu woke up but theres no vcpu to run");
@@ -56,7 +56,7 @@ static void psci_wake_from_powerdown()
     vcpu_run(cpu()->vcpu);
 }
 
-static void psci_wake_from_idle()
+static void psci_wake_from_idle(void)
 {
     cpu_idle_wakeup();
 }
diff --git a/src/arch/armv8/armv8-a/smmuv2.c b/src/arch/armv8/armv8-a/smmuv2.c
index 2948d551e..9e6734d6c 100644
--- a/src/arch/armv8/armv8-a/smmuv2.c
+++ b/src/arch/armv8/armv8-a/smmuv2.c
@@ -52,27 +52,27 @@ struct smmu_priv smmu;
 /**
  * Accessors inline functions.
  */
-inline bool smmu_sme_is_group(size_t sme)
+static inline bool smmu_sme_is_group(size_t sme)
 {
     return bitmap_get(smmu.grp_bitmap, sme);
 }
 
-inline size_t smmu_sme_get_ctx(size_t sme)
+static inline size_t smmu_sme_get_ctx(size_t sme)
 {
     return S2CR_CBNDX(smmu.hw.glbl_rs0->S2CR[sme]);
 }
 
-inline streamid_t smmu_sme_get_id(size_t sme)
+static inline streamid_t smmu_sme_get_id(size_t sme)
 {
     return SMMU_SMR_ID(smmu.hw.glbl_rs0->SMR[sme]);
 }
 
-inline streamid_t smmu_sme_get_mask(size_t sme)
+static inline streamid_t smmu_sme_get_mask(size_t sme)
 {
     return SMMU_SMR_MASK(smmu.hw.glbl_rs0->SMR[sme]);
 }
 
-static void smmu_check_features()
+static void smmu_check_features(void)
 {
     unsigned version =
         bit32_extract(smmu.hw.glbl_rs0->IDR7, SMMUV2_IDR7_MAJOR_OFF, SMMUV2_IDR7_MAJOR_LEN);
diff --git a/src/arch/armv8/armv8-r/inc/arch/mem.h b/src/arch/armv8/armv8-r/inc/arch/mem.h
index 1b3b300e2..cbeb2843b 100644
--- a/src/arch/armv8/armv8-r/inc/arch/mem.h
+++ b/src/arch/armv8/armv8-r/inc/arch/mem.h
@@ -52,7 +52,7 @@ typedef union {
 
 #define MPU_ARCH_MAX_NUM_ENTRIES (64)
 
-static inline size_t mpu_granularity()
+static inline size_t mpu_granularity(void)
 {
     return (size_t)PAGE_SIZE;
 }
diff --git a/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h b/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h
index 996c49a18..6f8f20479 100644
--- a/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h
+++ b/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h
@@ -38,7 +38,7 @@ struct cpu_arch_profile {
     } mpu;
 };
 
-static inline struct cpu* cpu()
+static inline struct cpu* cpu(void)
 {
     return (struct cpu*)sysreg_tpidr_el2_read();
 }
diff --git a/src/arch/armv8/armv8-r/mpu.c b/src/arch/armv8/armv8-r/mpu.c
index 2ef2502c1..d60c64f0c 100644
--- a/src/arch/armv8/armv8-r/mpu.c
+++ b/src/arch/armv8/armv8-r/mpu.c
@@ -8,7 +8,7 @@
 #include <arch/sysregs.h>
 #include <arch/fences.h>
 
-static inline size_t mpu_num_entries()
+static inline size_t mpu_num_entries(void)
 {
     return (size_t)MPUIR_REGION(sysreg_mpuir_el2_read());
 }
@@ -154,7 +154,7 @@ static inline mem_attrs_t mpu_entry_attrs(struct mp_region* mpr)
     return (mem_attrs_t)flags.raw;
 }
 
-static mpid_t mpu_entry_allocate()
+static mpid_t mpu_entry_allocate(void)
 {
     mpid_t reg_num = INVALID_MPID;
     for (mpid_t i = 0; i < (mpid_t)mpu_num_entries(); i++) {
diff --git a/src/arch/armv8/armv8-r/profile.mk b/src/arch/armv8/armv8-r/profile.mk
index a5d56125c..b9be93a96 100644
--- a/src/arch/armv8/armv8-r/profile.mk
+++ b/src/arch/armv8/armv8-r/profile.mk
@@ -2,7 +2,7 @@
 ## Copyright (c) Bao Project and Contributors. All rights reserved.
 
 arch-cppflags+= 
-arch-cflags+=-march=armv8-r -mgeneral-regs-only
+arch-cflags+=-march=armv8-r
 arch-asflags+=
 arch-ldflags+=
 
diff --git a/src/arch/armv8/asm_defs.c b/src/arch/armv8/asm_defs.c
index 44cbb2016..9bff72c0a 100644
--- a/src/arch/armv8/asm_defs.c
+++ b/src/arch/armv8/asm_defs.c
@@ -8,7 +8,7 @@
 #include <vm.h>
 #include <platform.h>
 
-__attribute__((used)) static void cpu_defines()
+__attribute__((used)) static void cpu_defines(void)
 {
     DEFINE_SIZE(CPU_SIZE, struct cpu);
 
@@ -18,14 +18,14 @@ __attribute__((used)) static void cpu_defines()
     DEFINE_OFFSET(CPU_VCPU_OFF, struct cpu, vcpu);
 }
 
-__attribute__((used)) static void vcpu_defines()
+__attribute__((used)) static void vcpu_defines(void)
 {
     DEFINE_SIZE(VCPU_ARCH_SIZE, struct vcpu_arch);
     DEFINE_OFFSET(VCPU_REGS_OFF, struct vcpu, regs);
     DEFINE_SIZE(VCPU_REGS_SIZE, struct arch_regs);
 }
 
-__attribute__((used)) static void platform_defines()
+__attribute__((used)) static void platform_defines(void)
 {
     DEFINE_OFFSET(PLAT_CPUNUM_OFF, struct platform, cpu_num);
     DEFINE_OFFSET(PLAT_ARCH_OFF, struct platform, arch);
diff --git a/src/arch/armv8/gic.c b/src/arch/armv8/gic.c
index 3867fd6d8..46018cfd6 100644
--- a/src/arch/armv8/gic.c
+++ b/src/arch/armv8/gic.c
@@ -22,7 +22,7 @@
 volatile struct gicd_hw* gicd;
 spinlock_t gicd_lock;
 
-static void gicd_init()
+static void gicd_init(void)
 {
     size_t int_num = gic_num_irqs();
 
@@ -69,9 +69,9 @@ static void gicd_init()
     }
 }
 
-void gic_map_mmio();
+void gic_map_mmio(void);
 
-void gic_init()
+void gic_init(void)
 {
     if (GIC_VERSION == GICV3) {
         sysreg_icc_sre_el2_write(ICC_SRE_SRE_BIT | ICC_SRE_ENB_BIT);
diff --git a/src/arch/armv8/gicv2.c b/src/arch/armv8/gicv2.c
index 69c2e8626..2af82214a 100644
--- a/src/arch/armv8/gicv2.c
+++ b/src/arch/armv8/gicv2.c
@@ -28,7 +28,7 @@ size_t gich_num_lrs()
     return ((gich->VTR & GICH_VTR_MSK) >> GICH_VTR_OFF) + 1;
 }
 
-static inline void gicc_init()
+static inline void gicc_init(void)
 {
     for (size_t i = 0; i < gich_num_lrs(); i++) {
         gich->LR[i] = 0;
diff --git a/src/arch/armv8/gicv3.c b/src/arch/armv8/gicv3.c
index bdf44d04e..37a87fe62 100644
--- a/src/arch/armv8/gicv3.c
+++ b/src/arch/armv8/gicv3.c
@@ -25,7 +25,7 @@ size_t gich_num_lrs(void)
     return ((sysreg_ich_vtr_el2_read() & ICH_VTR_MSK) >> ICH_VTR_OFF) + 1;
 }
 
-static inline void gicc_init()
+static inline void gicc_init(void)
 {
     for (size_t i = 0; i < gich_num_lrs(); i++) {
         gich_write_lr(i, 0);
@@ -38,7 +38,7 @@ static inline void gicc_init()
     sysreg_icc_igrpen1_el1_write(ICC_IGRPEN_EL1_ENB_BIT);
 }
 
-static inline void gicr_init()
+static inline void gicr_init(void)
 {
     gicr[cpu()->id].WAKER &= ~GICR_WAKER_ProcessorSleep_BIT;
     while (gicr[cpu()->id].WAKER & GICR_WAKER_ChildrenASleep_BIT) { }
diff --git a/src/arch/armv8/inc/arch/fences.h b/src/arch/armv8/inc/arch/fences.h
index 79239924c..d3d1daf46 100644
--- a/src/arch/armv8/inc/arch/fences.h
+++ b/src/arch/armv8/inc/arch/fences.h
@@ -14,32 +14,32 @@
 
 #define ISB()      __asm__ volatile("isb\n\t" ::: "memory")
 
-static inline void fence_ord_write()
+static inline void fence_ord_write(void)
 {
     DMB(ishst);
 }
 
-static inline void fence_ord_read()
+static inline void fence_ord_read(void)
 {
     DMB(ishld);
 }
 
-static inline void fence_ord()
+static inline void fence_ord(void)
 {
     DMB(ish);
 }
 
-static inline void fence_sync_write()
+static inline void fence_sync_write(void)
 {
     DSB(ishst);
 }
 
-static inline void fence_sync_read()
+static inline void fence_sync_read(void)
 {
     DSB(ishld);
 }
 
-static inline void fence_sync()
+static inline void fence_sync(void)
 {
     DSB(ish);
 }
diff --git a/src/arch/armv8/inc/arch/gic.h b/src/arch/armv8/inc/arch/gic.h
index 83423846f..65813c865 100644
--- a/src/arch/armv8/inc/arch/gic.h
+++ b/src/arch/armv8/inc/arch/gic.h
@@ -436,7 +436,7 @@ extern volatile struct gicr_hw* gicr;
 
 size_t gich_num_lrs(void);
 
-static inline size_t gic_num_irqs()
+static inline size_t gic_num_irqs(void)
 {
     size_t itlinenumber = bit32_extract(gicd->TYPER, GICD_TYPER_ITLN_OFF, GICD_TYPER_ITLN_LEN);
     return 32 * (itlinenumber + 1);
diff --git a/src/arch/armv8/inc/arch/gicv2.h b/src/arch/armv8/inc/arch/gicv2.h
index a1e6a85d1..2eb7a2092 100644
--- a/src/arch/armv8/inc/arch/gicv2.h
+++ b/src/arch/armv8/inc/arch/gicv2.h
@@ -26,7 +26,7 @@ static inline void gich_write_lr(size_t i, uint64_t val)
     }
 }
 
-static inline uint32_t gich_get_hcr()
+static inline uint32_t gich_get_hcr(void)
 {
     return gich->HCR;
 }
@@ -36,12 +36,12 @@ static inline void gich_set_hcr(uint32_t hcr)
     gich->HCR = hcr;
 }
 
-static inline uint32_t gich_get_misr()
+static inline uint32_t gich_get_misr(void)
 {
     return gich->MISR;
 }
 
-static inline uint64_t gich_get_eisr()
+static inline uint64_t gich_get_eisr(void)
 {
     uint64_t eisr = gich->EISR[0];
     if (NUM_LRS > 32) {
@@ -50,7 +50,7 @@ static inline uint64_t gich_get_eisr()
     return eisr;
 }
 
-static inline uint64_t gich_get_elrsr()
+static inline uint64_t gich_get_elrsr(void)
 {
     uint64_t elsr = gich->ELSR[0];
     if (NUM_LRS > 32) {
@@ -59,7 +59,7 @@ static inline uint64_t gich_get_elrsr()
     return elsr;
 }
 
-static inline uint32_t gicc_iar()
+static inline uint32_t gicc_iar(void)
 {
     return gicc->IAR;
 }
diff --git a/src/arch/armv8/inc/arch/gicv3.h b/src/arch/armv8/inc/arch/gicv3.h
index 25812cc92..1a86a1dfc 100644
--- a/src/arch/armv8/inc/arch/gicv3.h
+++ b/src/arch/armv8/inc/arch/gicv3.h
@@ -112,7 +112,7 @@ static inline void gich_write_lr(size_t i, uint64_t val)
     }
 }
 
-static inline uint32_t gich_get_hcr()
+static inline uint32_t gich_get_hcr(void)
 {
     return (uint32_t)sysreg_ich_hcr_el2_read();
 }
@@ -122,22 +122,22 @@ static inline void gich_set_hcr(uint32_t hcr)
     sysreg_ich_hcr_el2_write(hcr);
 }
 
-static inline uint32_t gich_get_misr()
+static inline uint32_t gich_get_misr(void)
 {
     return (uint32_t)sysreg_ich_misr_el2_read();
 }
 
-static inline uint64_t gich_get_eisr()
+static inline uint64_t gich_get_eisr(void)
 {
     return sysreg_ich_eisr_el2_read();
 }
 
-static inline uint64_t gich_get_elrsr()
+static inline uint64_t gich_get_elrsr(void)
 {
     return sysreg_ich_elrsr_el2_read();
 }
 
-static inline uint32_t gicc_iar()
+static inline uint32_t gicc_iar(void)
 {
     return (uint32_t)sysreg_icc_iar1_el1_read();
 }
diff --git a/src/arch/armv8/inc/arch/vm.h b/src/arch/armv8/inc/arch/vm.h
index bbd18b7af..7e63986e7 100644
--- a/src/arch/armv8/inc/arch/vm.h
+++ b/src/arch/armv8/inc/arch/vm.h
@@ -54,7 +54,7 @@ struct vcpu_arch {
 };
 
 struct vcpu* vm_get_vcpu_by_mpidr(struct vm* vm, unsigned long mpidr);
-void vcpu_arch_entry();
+void vcpu_arch_entry(void);
 
 bool vcpu_arch_profile_on(struct vcpu* vcpu);
 void vcpu_arch_profile_init(struct vcpu* vcpu, struct vm* vm);
diff --git a/src/arch/armv8/interrupts.c b/src/arch/armv8/interrupts.c
index 049e741f0..9d332e321 100644
--- a/src/arch/armv8/interrupts.c
+++ b/src/arch/armv8/interrupts.c
@@ -46,7 +46,7 @@ bool interrupts_arch_check(irqid_t int_id)
     return gic_get_pend(int_id);
 }
 
-inline bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id)
+bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id)
 {
     return (bitmap_get(interrupt_bitmap, int_id) && int_id > GIC_CPU_PRIV);
 }
diff --git a/src/arch/armv8/vgic.c b/src/arch/armv8/vgic.c
index 3f362da1a..8b96ff29b 100644
--- a/src/arch/armv8/vgic.c
+++ b/src/arch/armv8/vgic.c
@@ -44,7 +44,7 @@ extern volatile const size_t VGIC_IPI_ID;
 void vgic_ipi_handler(uint32_t event, uint64_t data);
 CPU_MSG_HANDLER(vgic_ipi_handler, VGIC_IPI_ID)
 
-inline struct vgic_int* vgic_get_int(struct vcpu* vcpu, irqid_t int_id, vcpuid_t vgicr_id)
+struct vgic_int* vgic_get_int(struct vcpu* vcpu, irqid_t int_id, vcpuid_t vgicr_id)
 {
     if (int_id < GIC_CPU_PRIV) {
         struct vcpu* target_vcpu = vgicr_id == vcpu->id ? vcpu : vm_get_vcpu(vcpu->vm, vgicr_id);
@@ -331,7 +331,7 @@ bool vgic_add_lr(struct vcpu* vcpu, struct vgic_int* interrupt)
     if (lr_ind < 0) {
         unsigned min_prio_pend = interrupt->prio, min_prio_act = interrupt->prio;
         unsigned min_id_act = interrupt->id, min_id_pend = interrupt->id;
-        size_t pend_found = 0, act_found = 0;
+        size_t pend_found = 0;
         ssize_t pend_ind = -1, act_ind = -1;
 
         for (size_t i = 0; i < NUM_LRS; i++) {
@@ -349,7 +349,6 @@ bool vgic_add_lr(struct vcpu* vcpu, struct vgic_int* interrupt)
                     min_prio_act = lr_prio;
                     act_ind = (ssize_t)i;
                 }
-                act_found++;
             } else if (lr_state & GICH_LR_STATE_PND) {
                 if (lr_prio > min_prio_pend || (lr_prio == min_prio_pend && lr_id > min_id_pend)) {
                     min_id_pend = lr_id;
diff --git a/src/arch/riscv/arch.mk b/src/arch/riscv/arch.mk
index 456babc30..deff44ae8 100644
--- a/src/arch/riscv/arch.mk
+++ b/src/arch/riscv/arch.mk
@@ -24,3 +24,5 @@ arch-ldflags =
 
 arch_mem_prot:=mmu
 PAGE_SIZE:=0x1000
+
+clang_arch_target:=riscv64
diff --git a/src/arch/riscv/asm_defs.c b/src/arch/riscv/asm_defs.c
index 2259e2642..6858f7463 100644
--- a/src/arch/riscv/asm_defs.c
+++ b/src/arch/riscv/asm_defs.c
@@ -8,7 +8,7 @@
 #include <vm.h>
 #include <platform.h>
 
-__attribute__((used)) static void cpu_defines()
+__attribute__((used)) static void cpu_defines(void)
 {
     DEFINE_SIZE(CPU_SIZE, struct cpu);
 
@@ -18,7 +18,7 @@ __attribute__((used)) static void cpu_defines()
     DEFINE_OFFSET(CPU_VCPU_OFF, struct cpu, vcpu);
 }
 
-__attribute__((used)) static void vcpu_defines()
+__attribute__((used)) static void vcpu_defines(void)
 {
     DEFINE_SIZE(VCPU_ARCH_SIZE, struct vcpu_arch);
     DEFINE_OFFSET(VCPU_REGS_OFF, struct vcpu, regs);
diff --git a/src/arch/riscv/boot.S b/src/arch/riscv/boot.S
index 0dbdb505f..98bf35b34 100644
--- a/src/arch/riscv/boot.S
+++ b/src/arch/riscv/boot.S
@@ -56,6 +56,7 @@ _dmem_beg_sym: .8byte _dmem_beg
 _enter_vas_sym: .8byte _enter_vas
 _bss_start_sym: .8byte _bss_start
 _bss_end_sym: .8byte _bss_end
+_extra_allocated_phys_mem_sym: .8byte extra_allocated_phys_mem
 
 .data 
 .align 3
@@ -90,7 +91,7 @@ _reset_handler:
 
     mv      a2, a1
     la      a1, _image_start
-    la      s6, extra_allocated_phys_mem
+    LD_SYM  s6, _extra_allocated_phys_mem_sym
 
     /**
      * Setup stvec early. In case of we cause an exception in this boot code we end up at a known
diff --git a/src/arch/riscv/inc/arch/cpu.h b/src/arch/riscv/inc/arch/cpu.h
index 3a5ca07c4..78b23451e 100644
--- a/src/arch/riscv/inc/arch/cpu.h
+++ b/src/arch/riscv/inc/arch/cpu.h
@@ -17,7 +17,7 @@ struct cpu_arch {
     unsigned plic_cntxt;
 };
 
-static inline struct cpu* cpu()
+static inline struct cpu* cpu(void)
 {
     return (struct cpu*)BAO_CPU_BASE;
 }
diff --git a/src/arch/riscv/inc/arch/fences.h b/src/arch/riscv/inc/arch/fences.h
index e5d8097a9..d82d8565f 100644
--- a/src/arch/riscv/inc/arch/fences.h
+++ b/src/arch/riscv/inc/arch/fences.h
@@ -5,32 +5,32 @@
 #ifndef __FENCES_ARCH_H__
 #define __FENCES_ARCH_H__
 
-static inline void fence_ord_write()
+static inline void fence_ord_write(void)
 {
     __asm__ volatile("fence w, rw\n\t" ::: "memory");
 }
 
-static inline void fence_ord_read()
+static inline void fence_ord_read(void)
 {
     __asm__ volatile("fence r, rw\n\t" ::: "memory");
 }
 
-static inline void fence_ord()
+static inline void fence_ord(void)
 {
     __asm__ volatile("fence rw, rw\n\t" ::: "memory");
 }
 
-static inline void fence_sync_write()
+static inline void fence_sync_write(void)
 {
     __asm__ volatile("fence ow, iorw\n\t" ::: "memory");
 }
 
-static inline void fence_sync_read()
+static inline void fence_sync_read(void)
 {
     __asm__ volatile("fence ir, iorw\n\t" ::: "memory");
 }
 
-static inline void fence_sync()
+static inline void fence_sync(void)
 {
     __asm__ volatile("fence iorw, iorw\n\t" ::: "memory");
 }
diff --git a/src/arch/riscv/inc/arch/tlb.h b/src/arch/riscv/inc/arch/tlb.h
index 21ba39723..1e50cfbdf 100644
--- a/src/arch/riscv/inc/arch/tlb.h
+++ b/src/arch/riscv/inc/arch/tlb.h
@@ -19,7 +19,7 @@ static inline void tlb_hyp_inv_va(vaddr_t va)
     sbi_remote_sfence_vma((1U << platform.cpu_num) - 1, 0, (unsigned long)va, PAGE_SIZE);
 }
 
-static inline void tlb_hyp_inv_all()
+static inline void tlb_hyp_inv_all(void)
 {
     sbi_remote_sfence_vma((1U << platform.cpu_num) - 1, 0, 0, 0);
 }
diff --git a/src/arch/riscv/inc/arch/vm.h b/src/arch/riscv/inc/arch/vm.h
index 3c1d63ec1..cabb0b893 100644
--- a/src/arch/riscv/inc/arch/vm.h
+++ b/src/arch/riscv/inc/arch/vm.h
@@ -125,7 +125,7 @@ struct arch_regs {
 
 } __attribute__((__packed__, aligned(sizeof(unsigned long))));
 
-void vcpu_arch_entry();
+void vcpu_arch_entry(void);
 
 static inline void vcpu_arch_inject_hw_irq(struct vcpu* vcpu, irqid_t id)
 {
diff --git a/src/arch/riscv/interrupts.c b/src/arch/riscv/interrupts.c
index 05bab96d8..05bf7ad30 100644
--- a/src/arch/riscv/interrupts.c
+++ b/src/arch/riscv/interrupts.c
@@ -119,7 +119,7 @@ void interrupts_arch_clear(irqid_t int_id)
     }
 }
 
-inline bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id)
+bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id)
 {
     return bitmap_get(interrupt_bitmap, int_id);
 }
diff --git a/src/arch/riscv/iommu.c b/src/arch/riscv/iommu.c
index 65b62f600..2b77d93dc 100644
--- a/src/arch/riscv/iommu.c
+++ b/src/arch/riscv/iommu.c
@@ -426,7 +426,7 @@ static bool iommu_vm_arch_add(struct vm* vm, deviceid_t dev_id)
  *
  * @returns true on success, false on error.
  */
-inline bool iommu_arch_vm_add_device(struct vm* vm, deviceid_t dev_id)
+bool iommu_arch_vm_add_device(struct vm* vm, deviceid_t dev_id)
 {
     return iommu_vm_arch_add(vm, dev_id);
 }
diff --git a/src/arch/riscv/irqc/aia/inc/irqc.h b/src/arch/riscv/irqc/aia/inc/irqc.h
index adbb5f0f6..edf84658e 100644
--- a/src/arch/riscv/irqc/aia/inc/irqc.h
+++ b/src/arch/riscv/irqc/aia/inc/irqc.h
@@ -19,12 +19,12 @@
 #define HYP_IRQ_SM_INACTIVE  APLIC_SOURCECFG_SM_INACTIVE
 #define HYP_IRQ_PRIO         APLIC_TARGET_MAX_PRIO
 
-static inline void irqc_init()
+static inline void irqc_init(void)
 {
     aplic_init();
 }
 
-static inline void irqc_cpu_init()
+static inline void irqc_cpu_init(void)
 {
     aplic_idc_init();
 }
@@ -41,7 +41,7 @@ static inline void irqc_config_irq(irqid_t int_id, bool en)
     }
 }
 
-static inline void irqc_handle()
+static inline void irqc_handle(void)
 {
     aplic_handle();
 }
diff --git a/src/arch/riscv/irqc/plic/inc/irqc.h b/src/arch/riscv/irqc/plic/inc/irqc.h
index d0e3ccc2c..ab6c0d4d4 100644
--- a/src/arch/riscv/irqc/plic/inc/irqc.h
+++ b/src/arch/riscv/irqc/plic/inc/irqc.h
@@ -16,12 +16,12 @@
 #define HART_REG_OFF        PLIC_THRESHOLD_OFF
 #define IRQC_HART_INST      PLIC_PLAT_CNTXT_NUM
 
-static inline void irqc_init()
+static inline void irqc_init(void)
 {
     plic_init();
 }
 
-static inline void irqc_cpu_init()
+static inline void irqc_cpu_init(void)
 {
     plic_cpu_init();
 }
@@ -32,7 +32,7 @@ static inline void irqc_config_irq(irqid_t int_id, bool en)
     plic_set_prio(int_id, 0xFE);
 }
 
-static inline void irqc_handle()
+static inline void irqc_handle(void)
 {
     plic_handle();
 }
diff --git a/src/arch/riscv/irqc/plic/plic.c b/src/arch/riscv/irqc/plic/plic.c
index 08b45c88f..795f91feb 100644
--- a/src/arch/riscv/irqc/plic/plic.c
+++ b/src/arch/riscv/irqc/plic/plic.c
@@ -14,7 +14,7 @@ volatile struct plic_global_hw* plic_global;
 
 volatile struct plic_hart_hw* plic_hart;
 
-static size_t plic_scan_max_int()
+static size_t plic_scan_max_int(void)
 {
     size_t res = 0;
     for (size_t i = 1; i < PLIC_MAX_INTERRUPTS; i++) {
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index 108880028..017f15957 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -213,10 +213,10 @@ static struct sbiret sbi_time_handler(unsigned long fid)
         csrs_sie_set(SIE_STIE);
     }
 
-    return (struct sbiret){ SBI_SUCCESS };
+    return (struct sbiret){ SBI_SUCCESS, 0 };
 }
 
-static void sbi_timer_irq_handler()
+static void sbi_timer_irq_handler(void)
 {
     csrs_hvip_set(HIP_VSTIP);
     csrs_sie_clear(SIE_STIE);
@@ -246,7 +246,7 @@ static struct sbiret sbi_ipi_handler(unsigned long fid)
         }
     }
 
-    return (struct sbiret){ SBI_SUCCESS };
+    return (struct sbiret){ SBI_SUCCESS, 0 };
 }
 
 static struct sbiret sbi_base_handler(unsigned long fid)
@@ -315,7 +315,7 @@ static struct sbiret sbi_rfence_handler(unsigned long fid)
     return ret;
 }
 
-static struct sbiret sbi_hsm_start_handler()
+static struct sbiret sbi_hsm_start_handler(void)
 {
     struct sbiret ret;
     vcpuid_t vhart_id = vcpu_readreg(cpu()->vcpu, REG_A0);
@@ -357,7 +357,7 @@ static struct sbiret sbi_hsm_start_handler()
     return ret;
 }
 
-static struct sbiret sbi_hsm_status_handler()
+static struct sbiret sbi_hsm_status_handler(void)
 {
     struct sbiret ret;
     vcpuid_t vhart_id = vcpu_readreg(cpu()->vcpu, REG_A0);
@@ -453,7 +453,7 @@ void sbi_init()
         }
     }
 
-    if (!interrupts_reserve(TIMR_INT_ID, sbi_timer_irq_handler)) {
+    if (!interrupts_reserve(TIMR_INT_ID, (irq_handler_t)sbi_timer_irq_handler)) {
         ERROR("Failed to reserve SBI TIMR_INT_ID interrupt");
     }
 }
diff --git a/src/arch/riscv/sync_exceptions.c b/src/arch/riscv/sync_exceptions.c
index cf3e1d2ef..e44c5414a 100644
--- a/src/arch/riscv/sync_exceptions.c
+++ b/src/arch/riscv/sync_exceptions.c
@@ -41,9 +41,9 @@ static uint32_t read_ins(uintptr_t ins_addr)
     return ins;
 }
 
-typedef size_t (*sync_handler_t)();
+typedef size_t (*sync_handler_t)(void);
 
-extern size_t sbi_vs_handler();
+extern size_t sbi_vs_handler(void);
 
 static inline bool ins_ldst_decode(vaddr_t ins, struct emul_access* emul)
 {
@@ -78,7 +78,7 @@ static inline bool is_pseudo_ins(uint32_t ins)
     return ins == TINST_PSEUDO_STORE || ins == TINST_PSEUDO_LOAD;
 }
 
-static size_t guest_page_fault_handler()
+static size_t guest_page_fault_handler(void)
 {
     vaddr_t addr = csrs_htval_read() << 2;
 
diff --git a/src/core/cpu.c b/src/core/cpu.c
index 68f30fa3c..efb103308 100644
--- a/src/core/cpu.c
+++ b/src/core/cpu.c
@@ -25,9 +25,9 @@ OBJPOOL_ALLOC(msg_pool, struct cpu_msg_node, CPU_MSG_POOL_SIZE);
 struct cpu_synctoken cpu_glb_sync = { .ready = false };
 
 extern cpu_msg_handler_t ipi_cpumsg_handlers[];
-extern uint8_t _ipi_cpumsg_handlers_size;
 extern size_t _ipi_cpumsg_handlers_id_start[];
-size_t ipi_cpumsg_handler_num;
+extern size_t _ipi_cpumsg_handlers_id_end[];
+static size_t ipi_cpumsg_handler_num;
 
 struct cpuif cpu_interfaces[PLAT_CPU_NUM];
 
@@ -44,7 +44,8 @@ void cpu_init(cpuid_t cpu_id, paddr_t load_addr)
     if (cpu_is_master()) {
         cpu_sync_init(&cpu_glb_sync, platform.cpu_num);
 
-        ipi_cpumsg_handler_num = ((size_t)&_ipi_cpumsg_handlers_size) / sizeof(cpu_msg_handler_t);
+        ipi_cpumsg_handler_num =
+            (size_t)(_ipi_cpumsg_handlers_id_end - _ipi_cpumsg_handlers_id_start);
         for (size_t i = 0; i < ipi_cpumsg_handler_num; i++) {
             ((size_t*)_ipi_cpumsg_handlers_id_start)[i] = i;
         }
diff --git a/src/core/inc/interrupts.h b/src/core/inc/interrupts.h
index a48efc527..b0e389be9 100644
--- a/src/core/inc/interrupts.h
+++ b/src/core/inc/interrupts.h
@@ -15,7 +15,7 @@ struct vm;
 
 typedef void (*irq_handler_t)(irqid_t int_id);
 
-void interrupts_init();
+void interrupts_init(void);
 bool interrupts_reserve(irqid_t int_id, irq_handler_t handler);
 
 void interrupts_cpu_sendipi(cpuid_t target_cpu, irqid_t ipi_id);
diff --git a/src/core/interrupts.c b/src/core/interrupts.c
index b3440f7b5..3ee9e972b 100644
--- a/src/core/interrupts.c
+++ b/src/core/interrupts.c
@@ -16,27 +16,27 @@ spinlock_t irq_reserve_lock = SPINLOCK_INITVAL;
 
 irq_handler_t interrupt_handlers[MAX_INTERRUPTS];
 
-inline void interrupts_cpu_sendipi(cpuid_t target_cpu, irqid_t ipi_id)
+void interrupts_cpu_sendipi(cpuid_t target_cpu, irqid_t ipi_id)
 {
     interrupts_arch_ipi_send(target_cpu, ipi_id);
 }
 
-inline void interrupts_cpu_enable(irqid_t int_id, bool en)
+void interrupts_cpu_enable(irqid_t int_id, bool en)
 {
     interrupts_arch_enable(int_id, en);
 }
 
-inline bool interrupts_check(irqid_t int_id)
+bool interrupts_check(irqid_t int_id)
 {
     return interrupts_arch_check(int_id);
 }
 
-inline void interrupts_clear(irqid_t int_id)
+void interrupts_clear(irqid_t int_id)
 {
     interrupts_arch_clear(int_id);
 }
 
-inline void interrupts_init()
+void interrupts_init(void)
 {
     interrupts_arch_init();
 
diff --git a/src/core/mpu/mem.c b/src/core/mpu/mem.c
index 0b3fd10c9..29b910e0c 100644
--- a/src/core/mpu/mem.c
+++ b/src/core/mpu/mem.c
@@ -125,7 +125,7 @@ static inline priv_t as_priv(struct addr_space* as)
     return priv;
 }
 
-static void as_init_boot_regions()
+static void as_init_boot_regions(void)
 {
     /**
      * Add hypervisor mpu entries set up during boot to the vmpu:
diff --git a/src/core/shmem.c b/src/core/shmem.c
index b89a96881..b3cdb19d0 100644
--- a/src/core/shmem.c
+++ b/src/core/shmem.c
@@ -9,7 +9,7 @@
 static size_t shmem_table_size;
 static struct shmem* shmem_table;
 
-static void shmem_alloc()
+static void shmem_alloc(void)
 {
     for (size_t i = 0; i < shmem_table_size; i++) {
         struct shmem* shmem = &shmem_table[i];
diff --git a/src/lib/inc/util.h b/src/lib/inc/util.h
index 2cbc6de69..063739306 100644
--- a/src/lib/inc/util.h
+++ b/src/lib/inc/util.h
@@ -34,10 +34,10 @@
 #ifndef __ASSEMBLER__
 
 #define DEFINE_OFFSET(SYMBOL, STRUCT, FIELD) \
-    __asm__ volatile("\n-> " XSTR(SYMBOL) " %0 \n" : : "i"(offsetof(STRUCT, FIELD)))
+    __asm__ volatile("\n##  " XSTR(SYMBOL) " %0 \n" : : "i"(offsetof(STRUCT, FIELD)))
 
 #define DEFINE_SIZE(SYMBOL, TYPE) \
-    __asm__ volatile("\n-> " XSTR(SYMBOL) " %0 \n" : : "i"(sizeof(TYPE)))
+    __asm__ volatile("\n##  " XSTR(SYMBOL) " %0 \n" : : "i"(sizeof(TYPE)))
 
 #define max(n1, n2) (((n1) > (n2)) ? (n1) : (n2))
 #define min(n1, n2) (((n1) < (n2)) ? (n1) : (n2))
diff --git a/src/lib/printk.c b/src/lib/printk.c
index e62fafa03..44292e01b 100644
--- a/src/lib/printk.c
+++ b/src/lib/printk.c
@@ -123,10 +123,10 @@ size_t vsnprintk(char* buf, size_t buf_size, const char** fmt, va_list* args)
                     case 'x':
                     case 'X':
                         flags = flags | F_BASE16;
-                    /* fallthrough */
+                        __attribute__((fallthrough));
                     case 'u':
                         flags = flags | F_UNSIGNED;
-                    /* fallthrough */
+                        __attribute__((fallthrough));
                     case 'd':
                     case 'i':
                         va_copy(args_tmp, *args);
diff --git a/src/linker.ld b/src/linker.ld
index 9418e4b7d..0c4bcea29 100644
--- a/src/linker.ld
+++ b/src/linker.ld
@@ -46,10 +46,9 @@ SECTIONS
 	.ipi_cpumsg_handlers_id : {
 		_ipi_cpumsg_handlers_id_start = .;
 		*(.ipi_cpumsg_handlers_id)
+        _ipi_cpumsg_handlers_id_end = .;
 	}
 
-	_ipi_cpumsg_handlers_size = SIZEOF(.ipi_cpumsg_handlers);
-
     . = ALIGN(PAGE_SIZE);
     _image_load_end = .;
 
diff --git a/src/platform/drivers/zynq_uart/zynq_uart.c b/src/platform/drivers/zynq_uart/zynq_uart.c
index 23f67fe22..be4cff47f 100644
--- a/src/platform/drivers/zynq_uart/zynq_uart.c
+++ b/src/platform/drivers/zynq_uart/zynq_uart.c
@@ -91,7 +91,7 @@ uint32_t uart_getc(volatile struct Uart_Zynq_hw* uart)
 
     // Chose one of the following: (Trigger Level or Not Empty)
     /* Wait until RxFIFO is filled up to the trigger level */
-    while (!uart->ch_status & UART_CH_STATUS_RTRIG) { }
+    while (!(uart->ch_status & UART_CH_STATUS_RTRIG)) { }
     /* Wait until RxFIFO is not empty */
     // while(!uart->ch_status & UART_CH_STATUS_REMPTY) { }