From 1c702f1298a1b9c8991fd31a50d96bb6e377a93f Mon Sep 17 00:00:00 2001 From: Bruno Sa Date: Fri, 20 Oct 2023 15:06:23 +0100 Subject: [PATCH 1/8] feat(clang): add llvm/clang support in makefile Signed-off-by: Bruno Sa Signed-off-by: David Cerdeira --- Makefile | 87 +++++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 23 deletions(-) diff --git a/Makefile b/Makefile index 0ce2a03e..030fd000 100644 --- a/Makefile +++ b/Makefile @@ -11,7 +11,27 @@ define current_directory $(realpath $(dir $(lastword $(MAKEFILE_LIST)))) endef +#Makefile arguments and default values +DEBUG:=y +OPTIMIZATIONS:=2 +CONFIG= +PLATFORM= +LLVM?= + # Setup toolchain macros + +ifneq ($(LLVM),) +cpp= $(LLVM)clang-cpp +sstrip= $(LLVM)llvm-strip +cc= $(LLVM)clang +ld = $(LLVM)ld.lld +as= $(LLVM)llvm-as +objcopy= $(LLVM)llvm-objcopy +objdump= $(LLVM)llvm-objdump +readelf= $(LLVM)llvm-readelf +size= $(LLVM)llvm-size +CC_IS_CLANG = y +else cpp= $(CROSS_COMPILE)cpp sstrip= $(CROSS_COMPILE)strip cc= $(CROSS_COMPILE)gcc @@ -21,14 +41,15 @@ objcopy= $(CROSS_COMPILE)objcopy objdump= $(CROSS_COMPILE)objdump readelf= $(CROSS_COMPILE)readelf size= $(CROSS_COMPILE)size +CC_IS_GCC = y +endif HOST_CC:=gcc -#Makefile arguments and default values -DEBUG:=n -OPTIMIZATIONS:=2 -CONFIG= -PLATFORM= +# Parse CLANG target +ifeq ($(CC_IS_CLANG),y) +CLANG_ARCH_TARGET := $(patsubst %-,%,$(lastword $(subst /, ,$(ARCH_TARGET)))) +endif # Setup version @@ -174,36 +195,56 @@ objs-y+=$(config_obj) build_macros:= ifeq ($(arch_mem_prot),mmu) -build_macros+=-DMEM_PROT_MMU + build_macros+=-DMEM_PROT_MMU endif ifeq ($(arch_mem_prot),mpu) -build_macros+=-DMEM_PROT_MPU + build_macros+=-DMEM_PROT_MPU +endif + +ifeq ($(CC_IS_GCC),y) + build_macros+=-DCC_IS_GCC +else ifeq ($(CC_IS_CLANG),y) + build_macros+=-DCC_IS_CLANG endif override CPPFLAGS+=$(addprefix -I, $(inc_dirs)) $(arch-cppflags) \ $(platform-cppflags) $(build_macros) vpath:.=CPPFLAGS +HOST_CPPFLAGS+=$(addprefix -I, $(inc_dirs)) $(arch-cppflags) \ + $(platform-cppflags) $(build_macros) + ifeq ($(DEBUG), y) debug_flags:=-g OPTIMIZATIONS:=g endif -cflags_warns:= \ - -Warith-conversion -Wbuiltin-declaration-mismatch \ - -Wcomments -Wdiscarded-qualifiers \ - -Wimplicit-fallthrough \ - -Wswitch-unreachable -Wreturn-local-addr \ - -Wshift-count-negative -Wuninitialized \ - -Wunused -Wunused-local-typedefs -Wunused-parameter \ - -Wunused-result -Wvla \ - -Wconversion -Wsign-conversion \ - -Wmissing-prototypes -Wmissing-declarations \ - -Wswitch-default -Wshadow -Wshadow=global \ - -Wcast-qual -Wunused-macros + +ifeq ($(CC_IS_GCC),y) + cflags_warns:= \ + -Warith-conversion -Wbuiltin-declaration-mismatch \ + -Wcomments -Wdiscarded-qualifiers \ + -Wimplicit-fallthrough \ + -Wswitch-unreachable -Wreturn-local-addr \ + -Wshift-count-negative -Wuninitialized \ + -Wunused -Wunused-local-typedefs -Wunused-parameter \ + -Wunused-result -Wvla \ + -Wconversion -Wsign-conversion \ + -Wmissing-prototypes -Wmissing-declarations \ + -Wswitch-default -Wshadow -Wshadow=global \ + -Wcast-qual -Wunused-macros + + override CFLAGS+=-Wno-unused-command-line-argument \ + -pedantic -pedantic-errors + override LDFLAGS+=--no-check-sections +else ifeq ($(CC_IS_CLANG), y) + override CFLAGS+=-Wno-unused-command-line-argument --target=$(CLANG_ARCH_TARGET) + override CPPFLAGS+=--target=$(CLANG_ARCH_TARGET) -ffreestanding + override LDFLAGS+=--no-check-sections +endif override CFLAGS+=-O$(OPTIMIZATIONS) -Wall -Werror -Wextra $(cflags_warns) \ - -ffreestanding -std=c11 -pedantic -pedantic-errors -fno-pic \ + -ffreestanding -std=c11 -fno-pic \ $(arch-cflags) $(platform-cflags) $(CPPFLAGS) $(debug_flags) override ASFLAGS+=$(CFLAGS) $(arch-asflags) $(platform-asflags) @@ -264,7 +305,7 @@ ifneq ($(wildcard $(asm_defs_src)),) $(asm_defs_hdr): $(asm_defs_src) @echo "Generating header $(patsubst $(cur_dir)/%, %, $@)" @$(cc) -S $(CFLAGS) -DGENERATING_DEFS $< -o - \ - | awk '($$1 == "->") \ + | awk '($$1 == "//#" || $$1 == "##") \ { gsub("#", "", $$3); print "#define " $$2 " " $$3 }' > $@ $(asm_defs_hdr).d: $(asm_defs_src) @@ -282,7 +323,7 @@ $(config_dep): $(config_src) $(config_def_generator): $(config_def_generator_src) $(config_src) @echo "Compiling generator $(patsubst $(cur_dir)/%, %, $@)" - @$(HOST_CC) $^ $(build_macros) $(CPPFLAGS) -DGENERATING_DEFS \ + @$(HOST_CC) $^ $(build_macros) $(HOST_CPPFLAGS) -DGENERATING_DEFS \ $(addprefix -I, $(inc_dirs)) -o $@ $(config_defs): $(config_def_generator) @@ -291,7 +332,7 @@ $(config_defs): $(config_def_generator) $(platform_def_generator): $(platform_def_generator_src) $(platform_description) @echo "Compiling generator $(patsubst $(cur_dir)/%, %, $@)" - @$(HOST_CC) $^ $(build_macros) $(CPPFLAGS) -DGENERATING_DEFS -D$(ARCH) \ + @$(HOST_CC) $^ $(build_macros) $(HOST_CPPFLAGS) -DGENERATING_DEFS -D$(ARCH) \ $(addprefix -I, $(inc_dirs)) -o $@ $(platform_defs): $(platform_def_generator) From 6666cdbf43a2d804f323b3d74daea3bf8310493e Mon Sep 17 00:00:00 2001 From: Bruno Sa Date: Fri, 20 Oct 2023 15:17:24 +0100 Subject: [PATCH 2/8] feat(clang): refactor headers generation for clang Clang assembler requires valid assembly; otherwise, an error is thrown. Instead of using "->" as the token to parse for assembly macro defines, we define the tokens "#", which is used for comments in assembly files. The generated output will be valid for both clang and gcc. Signed-off-by: Bruno Sa --- src/lib/inc/util.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/inc/util.h b/src/lib/inc/util.h index 2cbc6de6..06373930 100644 --- a/src/lib/inc/util.h +++ b/src/lib/inc/util.h @@ -34,10 +34,10 @@ #ifndef __ASSEMBLER__ #define DEFINE_OFFSET(SYMBOL, STRUCT, FIELD) \ - __asm__ volatile("\n-> " XSTR(SYMBOL) " %0 \n" : : "i"(offsetof(STRUCT, FIELD))) + __asm__ volatile("\n## " XSTR(SYMBOL) " %0 \n" : : "i"(offsetof(STRUCT, FIELD))) #define DEFINE_SIZE(SYMBOL, TYPE) \ - __asm__ volatile("\n-> " XSTR(SYMBOL) " %0 \n" : : "i"(sizeof(TYPE))) + __asm__ volatile("\n## " XSTR(SYMBOL) " %0 \n" : : "i"(sizeof(TYPE))) #define max(n1, n2) (((n1) > (n2)) ? (n1) : (n2)) #define min(n1, n2) (((n1) < (n2)) ? (n1) : (n2)) From 29beb3554859ea3a297072091f6e1f38608d073e Mon Sep 17 00:00:00 2001 From: Bruno Sa Date: Fri, 20 Oct 2023 15:18:41 +0100 Subject: [PATCH 3/8] feat(clang): add support for riscv clang This commit fixes relocation errors identified by the clang compiler and marks the .gtl_page_tables section as no data otherwise there is a type mismatch. Signed-off-by: Bruno Sa --- src/arch/riscv/boot.S | 2 ++ src/arch/riscv/root_pt.S | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/boot.S b/src/arch/riscv/boot.S index 0dbdb505..96367e7a 100644 --- a/src/arch/riscv/boot.S +++ b/src/arch/riscv/boot.S @@ -56,6 +56,7 @@ _dmem_beg_sym: .8byte _dmem_beg _enter_vas_sym: .8byte _enter_vas _bss_start_sym: .8byte _bss_start _bss_end_sym: .8byte _bss_end +_extra_allocated_phys_mem_sym: .8byte extra_allocated_phys_mem .data .align 3 @@ -90,6 +91,7 @@ _reset_handler: mv a2, a1 la a1, _image_start + LD_SYM s6, _extra_allocated_phys_mem_sym la s6, extra_allocated_phys_mem /** diff --git a/src/arch/riscv/root_pt.S b/src/arch/riscv/root_pt.S index 7b6a3252..fecc0725 100644 --- a/src/arch/riscv/root_pt.S +++ b/src/arch/riscv/root_pt.S @@ -5,7 +5,7 @@ #include -.section .glb_page_tables, "aw" +.section .glb_page_tables, "aw",@nobits .globl root_l1_pt .balign PAGE_SIZE, 0 From b11b41389006eeecb09998b7c5cc85394c889b2d Mon Sep 17 00:00:00 2001 From: David Cerdeira Date: Thu, 25 Jul 2024 11:10:44 +0100 Subject: [PATCH 4/8] feat(clang): add support for armv8 clang This commit fixes some issues when using clang: - remove .directive .func which is not recognized by clang assembler; - make gtlb_page_tables as no data to avoid section type mismatch; - remove general-regs-only in aarch32 this is not recognized by the clang assembler - remove mov instructions with flexible second operand since they are not recognized by the clang assembler; Signed-off-by: Bruno Sa Signed-off-by: David Cerdeira --- src/arch/armv8/aarch32/boot.S | 8 ++++ src/arch/armv8/aarch64/boot.S | 8 ++++ src/arch/armv8/arch.mk | 2 + src/arch/armv8/armv8-a/aarch64/boot.S | 54 ++++++++++++++------------- src/arch/armv8/armv8-a/pagetables.S | 2 +- src/arch/armv8/armv8-r/profile.mk | 5 ++- 6 files changed, 52 insertions(+), 27 deletions(-) diff --git a/src/arch/armv8/aarch32/boot.S b/src/arch/armv8/aarch32/boot.S index 0b613c22..53d6a0e5 100644 --- a/src/arch/armv8/aarch32/boot.S +++ b/src/arch/armv8/aarch32/boot.S @@ -184,7 +184,9 @@ _set_master_cpu: /***** Helper functions for boot code. ******/ .global boot_clear +#ifdef CC_IS_GCC .func boot_clear +#endif boot_clear: 2: mov r8, #0 @@ -195,7 +197,9 @@ boot_clear: b 2b 1: bx lr +#ifdef CC_IS_GCC .endfunc +#endif /* * Code adapted from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0" @@ -203,7 +207,9 @@ boot_clear: * r0 - cache level to be invalidated (0 - dl1$, 1 - il1$) */ .global boot_cache_invalidate +#ifdef CC_IS_GCC .func boot_cache_invalidate +#endif boot_cache_invalidate: mcr p15, 2, r0, c0, c0, 0 // write CSSELR (cache size selection) mrc p15, 1, r4, c0, c0, 0 // read CCSIDR (cache size id) @@ -230,5 +236,7 @@ set_loop: cmp r5, r3 // last way reached yet? ble way_loop // if not, iterate way_loop bx lr +#ifdef CC_IS_GCC .endfunc +#endif diff --git a/src/arch/armv8/aarch64/boot.S b/src/arch/armv8/aarch64/boot.S index 5c2a159c..5c32c788 100644 --- a/src/arch/armv8/aarch64/boot.S +++ b/src/arch/armv8/aarch64/boot.S @@ -180,7 +180,9 @@ _set_master_cpu: /***** Helper functions for boot code. ******/ .global boot_clear +#ifdef CC_IS_GCC .func boot_clear +#endif boot_clear: 2: cmp x16, x17 @@ -189,7 +191,9 @@ boot_clear: b 2b 1: ret +#ifdef CC_IS_GCC .endfunc +#endif /* * Code taken from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0" @@ -197,7 +201,9 @@ boot_clear: * x0 - cache level to be invalidated (0 - dl1$, 1 - il1$, 2 - l2$) */ .global boot_cache_invalidate +#ifdef CC_IS_GCC .func boot_cache_invalidate +#endif boot_cache_invalidate: msr csselr_el1, x0 mrs x4, ccsidr_el1 // read cache size id. @@ -224,6 +230,8 @@ set_loop: cmp x5, x3 // last way reached yet? ble way_loop // if not, iterate way_loop ret +#ifdef CC_IS_GCC .endfunc +#endif diff --git a/src/arch/armv8/arch.mk b/src/arch/armv8/arch.mk index c42158b2..9aa50a74 100644 --- a/src/arch/armv8/arch.mk +++ b/src/arch/armv8/arch.mk @@ -15,6 +15,8 @@ arch_profile_sub_dir:=$(arch_profile_dir)/$(ARCH_SUB) src_dirs+=$(arch_profile_sub_dir) arch-cppflags+=-DGIC_VERSION=$(GIC_VERSION) +ifeq ($(CC_IS_GCC),y) arch-cflags+=-mgeneral-regs-only +endif arch-asflags+= arch-ldflags+= diff --git a/src/arch/armv8/armv8-a/aarch64/boot.S b/src/arch/armv8/armv8-a/aarch64/boot.S index 708d6ba1..89b2d2b0 100644 --- a/src/arch/armv8/armv8-a/aarch64/boot.S +++ b/src/arch/armv8/armv8-a/aarch64/boot.S @@ -24,27 +24,27 @@ boot_arch_profile_init: ldr x18, =extra_allocated_phys_mem /* Disable caches and MMU */ - mrs x3, SCTLR_EL2 - bic x3, x3, #0x7 - msr SCTLR_EL2, x3 - + mrs x3, SCTLR_EL2 + bic x3, x3, #0x7 + msr SCTLR_EL2, x3 + /* Skip initialy global page tables setup if not bsp (boot cpu) */ cbnz x9, wait_for_bsp - adr x16, _page_tables_start - adr x17, _page_tables_end + adr x16, _page_tables_start + adr x17, _page_tables_end add x16, x16, x18 add x17, x17, x18 - bl boot_clear + bl boot_clear /* Set temporary flat mapping to switch to VAS. */ adr x4, root_l1_flat_pt add x4, x4, x18 - PTE_INDEX_ASM x5, x1, 1 + PTE_INDEX_ASM x5, x1, 1 add x6, x1, #(PTE_HYP_FLAGS | PTE_SUPERPAGE) str x6, [x4, x5] - + /* Set global root mappings for hypervisor image */ adr x4, root_l1_pt @@ -96,7 +96,7 @@ boot_arch_profile_init: sev b map_cpu -wait_for_bsp: +wait_for_bsp: /* wait fot the bsp to finish up global mappings */ wfe ldr x4, _boot_barrier @@ -110,15 +110,15 @@ map_cpu: * x5 -> pte index * x6 -> phys addr * x7 -> virt addr - * x8 -> aux + * x8 -> aux */ /* get cpu root pt */ adrp x3, _dmem_phys_beg mov x8, #(CPU_SIZE + (PT_SIZE*PT_LVLS)) madd x3, x0, x8, x3 - - mov x16, x3 + + mov x16, x3 add x17, x3, x8 bl boot_clear @@ -126,12 +126,12 @@ map_cpu: add x4, x3, #CPU_SIZE /* map original bootstrap flat mappings */ - PTE_INDEX_ASM x5, x1, 0 + PTE_INDEX_ASM x5, x1, 0 adr x6, root_l1_flat_pt add x6, x6, x18 add x6, x6, #(PTE_HYP_FLAGS | PTE_TABLE) str x6, [x4, x5] - + ldr x5, =(PTE_INDEX(0, BAO_VAS_BASE)*8) adr x6, root_l1_pt add x6, x6, x18 @@ -174,7 +174,7 @@ setup_cpu: /** * The operation is purposely commented out. We are assuming monitor code already enabled smp * coherency. - */ + */ /* setup translation configurations */ ldr x3, =TCR_EL2_DFLT @@ -194,7 +194,7 @@ setup_cpu: add x3, x3, #CPU_SIZE msr TTBR0_EL2, x3 - /** + /** * TODO: set implementation defined registers such as ACTLR or AMAIR. Maybe define a macro for * this in a implementation oriented directory inside arch. */ @@ -208,11 +208,11 @@ setup_cpu: /* Enable MMU and caches */ ldr x4, =(SCTLR_RES1 | SCTLR_M | SCTLR_C | SCTLR_I) msr SCTLR_EL2, x4 - + tlbi alle2 dsb nsh isb - + br x5 _enter_vas: @@ -224,7 +224,7 @@ _enter_vas: /* Remove temporary mapping - the L1 page holding it leaks */ ldr x4, =BAO_CPU_BASE add x4, x4, #CPU_SIZE - PTE_INDEX_ASM x5, x1, 0 + PTE_INDEX_ASM x5, x1, 0 str xzr, [x4, x5] tlbi alle2 @@ -237,7 +237,9 @@ _enter_vas: ret .global psci_boot_entry +#ifdef CC_IS_GCC .func psci_boot_entry +#endif psci_boot_entry: warm_boot: @@ -272,7 +274,7 @@ warm_boot: /* map original bootstrap flat mappings */ mrs x3, TTBR0_EL2 adrp x1, _image_start - PTE_INDEX_ASM x1, x1, 0 + PTE_INDEX_ASM x1, x1, 0 add x3, x3, x1 dc civac, x3 //we invalidated l1$, but make sure the pte is not in l2$ add x5, x5, #(PTE_HYP_FLAGS | PTE_TABLE) @@ -282,7 +284,7 @@ warm_boot: ldr x3, =_hyp_vector_table msr VBAR_EL2, x3 - tlbi alle2 + tlbi alle2 dsb nsh isb @@ -292,9 +294,9 @@ warm_boot: dsb nsh isb - + ldr x5, =_enter_vas_warm - br x5 + br x5 _enter_vas_warm: /* Unmap bootstrat flat mappings */ @@ -302,7 +304,7 @@ _enter_vas_warm: add x3, x4, #(CPU_STACK_OFF+CPU_STACK_SIZE) add x4, x4, #CPU_SIZE - PTE_INDEX_ASM x5, x1, 0 + PTE_INDEX_ASM x5, x1, 0 str xzr, [x4, x5] tlbi alle2 dsb nsh @@ -314,4 +316,6 @@ _enter_vas_warm: bl psci_wake b . +#ifdef CC_IS_GCC .endfunc +#endif diff --git a/src/arch/armv8/armv8-a/pagetables.S b/src/arch/armv8/armv8-a/pagetables.S index f9dd4f19..1f4b6a74 100644 --- a/src/arch/armv8/armv8-a/pagetables.S +++ b/src/arch/armv8/armv8-a/pagetables.S @@ -5,7 +5,7 @@ #include -.section .glb_page_tables, "aw" +.section .glb_page_tables, "aw", %nobits .globl root_l1_pt .balign PAGE_SIZE, 0 diff --git a/src/arch/armv8/armv8-r/profile.mk b/src/arch/armv8/armv8-r/profile.mk index a5d56125..2828083b 100644 --- a/src/arch/armv8/armv8-r/profile.mk +++ b/src/arch/armv8/armv8-r/profile.mk @@ -2,7 +2,10 @@ ## Copyright (c) Bao Project and Contributors. All rights reserved. arch-cppflags+= -arch-cflags+=-march=armv8-r -mgeneral-regs-only +arch-cflags+=-march=armv8-r +ifeq ($(CC_IS_GCC),y) + arch-cflags+=-mgeneral-regs-only +endif arch-asflags+= arch-ldflags+= From 36bee043ef72b46714aefedc4cdec52b7758767c Mon Sep 17 00:00:00 2001 From: Miguel Silva Date: Fri, 26 Jul 2024 10:55:56 +0100 Subject: [PATCH 5/8] feat(flags): Add warning flags to Makefile These flags are enabled in Clang compiler by default. Adding these flags minimized the discrepancies between GCC and Clang Signed-off-by: Miguel Silva --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 030fd000..41d48d59 100644 --- a/Makefile +++ b/Makefile @@ -232,7 +232,8 @@ ifeq ($(CC_IS_GCC),y) -Wconversion -Wsign-conversion \ -Wmissing-prototypes -Wmissing-declarations \ -Wswitch-default -Wshadow -Wshadow=global \ - -Wcast-qual -Wunused-macros + -Wcast-qual -Wunused-macros \ + -Wstrict-prototypes -Wunused-but-set-variable override CFLAGS+=-Wno-unused-command-line-argument \ -pedantic -pedantic-errors From 1785ca071afa93dab7835fb7b529120dcb5c9a8e Mon Sep 17 00:00:00 2001 From: Miguel Silva Date: Wed, 24 Jul 2024 13:57:46 +0100 Subject: [PATCH 6/8] feat(missing-void): Add missing void argument to function prototypes Signed-off-by: Miguel Silva --- ci | 2 +- src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h | 12 ++++++------ src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h | 6 +++--- src/arch/armv8/armv8-a/inc/arch/profile/cpu.h | 2 +- src/arch/armv8/armv8-a/inc/arch/tlb.h | 2 +- src/arch/armv8/armv8-a/psci.c | 6 +++--- src/arch/armv8/armv8-a/smmuv2.c | 2 +- src/arch/armv8/armv8-r/inc/arch/mem.h | 2 +- src/arch/armv8/armv8-r/inc/arch/profile/cpu.h | 2 +- src/arch/armv8/armv8-r/mpu.c | 4 ++-- src/arch/armv8/asm_defs.c | 6 +++--- src/arch/armv8/gic.c | 6 +++--- src/arch/armv8/gicv2.c | 2 +- src/arch/armv8/gicv3.c | 4 ++-- src/arch/armv8/inc/arch/fences.h | 12 ++++++------ src/arch/armv8/inc/arch/gic.h | 2 +- src/arch/armv8/inc/arch/gicv2.h | 10 +++++----- src/arch/armv8/inc/arch/gicv3.h | 10 +++++----- src/arch/armv8/inc/arch/vm.h | 2 +- src/arch/riscv/asm_defs.c | 4 ++-- src/arch/riscv/inc/arch/cpu.h | 2 +- src/arch/riscv/inc/arch/fences.h | 12 ++++++------ src/arch/riscv/inc/arch/tlb.h | 2 +- src/arch/riscv/inc/arch/vm.h | 2 +- src/arch/riscv/irqc/aia/inc/irqc.h | 6 +++--- src/arch/riscv/irqc/plic/inc/irqc.h | 6 +++--- src/arch/riscv/irqc/plic/plic.c | 2 +- src/arch/riscv/sbi.c | 8 ++++---- src/arch/riscv/sync_exceptions.c | 6 +++--- src/core/inc/interrupts.h | 2 +- src/core/interrupts.c | 2 +- src/core/mpu/mem.c | 2 +- src/core/shmem.c | 2 +- 33 files changed, 76 insertions(+), 76 deletions(-) diff --git a/ci b/ci index f0fba61d..3ef5099b 160000 --- a/ci +++ b/ci @@ -1 +1 @@ -Subproject commit f0fba61d699a73f5f658bde40cbc8b7f6803d2c2 +Subproject commit 3ef5099b3c15be813ebde724ccdaae18b2a0dfe2 diff --git a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h index aac8e17b..d35c59d9 100644 --- a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h +++ b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h @@ -11,7 +11,7 @@ #ifndef __ASSEMBLER__ #define SYSREG_GEN_ACCESSORS(name, op1, crn, crm, op2) \ - static inline unsigned long sysreg_##name##_read() \ + static inline unsigned long sysreg_##name##_read(void) \ { \ unsigned long _temp; \ __asm__ volatile("mrc p15, " #op1 ", %0, " #crn ", " #crm ", %1\n\r" : "=r"(_temp) \ @@ -24,7 +24,7 @@ } #define SYSREG_GEN_ACCESSORS_BANKED(name, reg) \ - static inline unsigned long sysreg_##name##_read() \ + static inline unsigned long sysreg_##name##_read(void) \ { \ unsigned long _temp; \ __asm__ volatile("mrs %0, " XSTR(reg) "\n\r" : "=r"(_temp)); \ @@ -36,7 +36,7 @@ } #define SYSREG_GEN_ACCESSORS_64(reg, op1, crm) \ - static inline unsigned long long sysreg_##reg##_read() \ + static inline unsigned long long sysreg_##reg##_read(void) \ { \ unsigned long long _temp, _tempH; \ __asm__ volatile("mrrc p15, " #op1 ", %0, %1, " #crm "\n\r" : "=r"(_temp), "=r"(_tempH)); \ @@ -49,7 +49,7 @@ } #define SYSREG_GEN_ACCESSORS_MERGE(reg, reg1, reg2) \ - static inline unsigned long long sysreg_##reg##_read() \ + static inline unsigned long long sysreg_##reg##_read(void) \ { \ return ((unsigned long long)sysreg_##reg2##_read() << 32) | sysreg_##reg1##_read(); \ } \ @@ -155,12 +155,12 @@ static inline void arm_at_s12e1w(vaddr_t vaddr) __asm__ volatile("mcr p15, 0, %0, c7, c8, 5" ::"r"(vaddr)); // ats12nsopw } -static inline void arm_tlbi_alle2is() +static inline void arm_tlbi_alle2is(void) { __asm__ volatile("mcr p15, 4, r0, c8, c7, 0"); } -static inline void arm_tlbi_vmalls12e1is() +static inline void arm_tlbi_vmalls12e1is(void) { __asm__ volatile("mcr p15, 0, r0, c8, c7, 0"); } diff --git a/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h b/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h index ba2f609e..0dbf632c 100644 --- a/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h +++ b/src/arch/armv8/aarch64/inc/arch/subarch/sysregs.h @@ -47,7 +47,7 @@ #ifndef __ASSEMBLER__ #define SYSREG_GEN_ACCESSORS_NAME(reg, name) \ - static inline unsigned long sysreg##reg##read() \ + static inline unsigned long sysreg##reg##read(void) \ { \ unsigned long _temp; \ __asm__ volatile("mrs %0, " XSTR(name) "\n\r" : "=r"(_temp)); \ @@ -138,12 +138,12 @@ static inline void arm_at_s12e1w(vaddr_t vaddr) __asm__ volatile("at s12e1w, %0" ::"r"(vaddr)); } -static inline void arm_tlbi_alle2is() +static inline void arm_tlbi_alle2is(void) { __asm__ volatile("tlbi alle2is"); } -static inline void arm_tlbi_vmalls12e1is() +static inline void arm_tlbi_vmalls12e1is(void) { __asm__ volatile("tlbi vmalls12e1is"); } diff --git a/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h b/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h index a7286364..78932452 100644 --- a/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h +++ b/src/arch/armv8/armv8-a/inc/arch/profile/cpu.h @@ -13,7 +13,7 @@ struct cpu_arch_profile { struct psci_off_state psci_off_state; }; -static inline struct cpu* cpu() +static inline struct cpu* cpu(void) { return (struct cpu*)BAO_CPU_BASE; } diff --git a/src/arch/armv8/armv8-a/inc/arch/tlb.h b/src/arch/armv8/armv8-a/inc/arch/tlb.h index 6edd4a3e..d6608fe8 100644 --- a/src/arch/armv8/armv8-a/inc/arch/tlb.h +++ b/src/arch/armv8/armv8-a/inc/arch/tlb.h @@ -18,7 +18,7 @@ static inline void tlb_hyp_inv_va(vaddr_t va) ISB(); } -static inline void tlb_hyp_inv_all() +static inline void tlb_hyp_inv_all(void) { DSB(ish); arm_tlbi_alle2is(); diff --git a/src/arch/armv8/armv8-a/psci.c b/src/arch/armv8/armv8-a/psci.c index 6a378bba..da8cf041 100644 --- a/src/arch/armv8/armv8-a/psci.c +++ b/src/arch/armv8/armv8-a/psci.c @@ -36,7 +36,7 @@ static void psci_save_state(enum wakeup_reason wakeup_reason) gicc_save_state(&cpu()->arch.profile.psci_off_state.gicc_state); } -static void psci_restore_state() +static void psci_restore_state(void) { /** * The majority of the state is already restored in assembly routine psci_boot_entry. @@ -45,7 +45,7 @@ static void psci_restore_state() gicc_restore_state(&cpu()->arch.profile.psci_off_state.gicc_state); } -static void psci_wake_from_powerdown() +static void psci_wake_from_powerdown(void) { if (cpu()->vcpu == NULL) { ERROR("cpu woke up but theres no vcpu to run"); @@ -56,7 +56,7 @@ static void psci_wake_from_powerdown() vcpu_run(cpu()->vcpu); } -static void psci_wake_from_idle() +static void psci_wake_from_idle(void) { cpu_idle_wakeup(); } diff --git a/src/arch/armv8/armv8-a/smmuv2.c b/src/arch/armv8/armv8-a/smmuv2.c index 2948d551..e942577f 100644 --- a/src/arch/armv8/armv8-a/smmuv2.c +++ b/src/arch/armv8/armv8-a/smmuv2.c @@ -72,7 +72,7 @@ inline streamid_t smmu_sme_get_mask(size_t sme) return SMMU_SMR_MASK(smmu.hw.glbl_rs0->SMR[sme]); } -static void smmu_check_features() +static void smmu_check_features(void) { unsigned version = bit32_extract(smmu.hw.glbl_rs0->IDR7, SMMUV2_IDR7_MAJOR_OFF, SMMUV2_IDR7_MAJOR_LEN); diff --git a/src/arch/armv8/armv8-r/inc/arch/mem.h b/src/arch/armv8/armv8-r/inc/arch/mem.h index 1b3b300e..cbeb2843 100644 --- a/src/arch/armv8/armv8-r/inc/arch/mem.h +++ b/src/arch/armv8/armv8-r/inc/arch/mem.h @@ -52,7 +52,7 @@ typedef union { #define MPU_ARCH_MAX_NUM_ENTRIES (64) -static inline size_t mpu_granularity() +static inline size_t mpu_granularity(void) { return (size_t)PAGE_SIZE; } diff --git a/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h b/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h index 996c49a1..6f8f2047 100644 --- a/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h +++ b/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h @@ -38,7 +38,7 @@ struct cpu_arch_profile { } mpu; }; -static inline struct cpu* cpu() +static inline struct cpu* cpu(void) { return (struct cpu*)sysreg_tpidr_el2_read(); } diff --git a/src/arch/armv8/armv8-r/mpu.c b/src/arch/armv8/armv8-r/mpu.c index 8acf13fe..db0ae283 100644 --- a/src/arch/armv8/armv8-r/mpu.c +++ b/src/arch/armv8/armv8-r/mpu.c @@ -8,7 +8,7 @@ #include #include -static inline size_t mpu_num_entries() +static inline size_t mpu_num_entries(void) { return (size_t)MPUIR_REGION(sysreg_mpuir_el2_read()); } @@ -154,7 +154,7 @@ static inline mem_attrs_t mpu_entry_attrs(struct mp_region* mpr) return (mem_attrs_t)flags.raw; } -static mpid_t mpu_entry_allocate() +static mpid_t mpu_entry_allocate(void) { mpid_t reg_num = INVALID_MPID; for (mpid_t i = 0; i < (mpid_t)mpu_num_entries(); i++) { diff --git a/src/arch/armv8/asm_defs.c b/src/arch/armv8/asm_defs.c index 44cbb201..9bff72c0 100644 --- a/src/arch/armv8/asm_defs.c +++ b/src/arch/armv8/asm_defs.c @@ -8,7 +8,7 @@ #include #include -__attribute__((used)) static void cpu_defines() +__attribute__((used)) static void cpu_defines(void) { DEFINE_SIZE(CPU_SIZE, struct cpu); @@ -18,14 +18,14 @@ __attribute__((used)) static void cpu_defines() DEFINE_OFFSET(CPU_VCPU_OFF, struct cpu, vcpu); } -__attribute__((used)) static void vcpu_defines() +__attribute__((used)) static void vcpu_defines(void) { DEFINE_SIZE(VCPU_ARCH_SIZE, struct vcpu_arch); DEFINE_OFFSET(VCPU_REGS_OFF, struct vcpu, regs); DEFINE_SIZE(VCPU_REGS_SIZE, struct arch_regs); } -__attribute__((used)) static void platform_defines() +__attribute__((used)) static void platform_defines(void) { DEFINE_OFFSET(PLAT_CPUNUM_OFF, struct platform, cpu_num); DEFINE_OFFSET(PLAT_ARCH_OFF, struct platform, arch); diff --git a/src/arch/armv8/gic.c b/src/arch/armv8/gic.c index 3867fd6d..46018cfd 100644 --- a/src/arch/armv8/gic.c +++ b/src/arch/armv8/gic.c @@ -22,7 +22,7 @@ volatile struct gicd_hw* gicd; spinlock_t gicd_lock; -static void gicd_init() +static void gicd_init(void) { size_t int_num = gic_num_irqs(); @@ -69,9 +69,9 @@ static void gicd_init() } } -void gic_map_mmio(); +void gic_map_mmio(void); -void gic_init() +void gic_init(void) { if (GIC_VERSION == GICV3) { sysreg_icc_sre_el2_write(ICC_SRE_SRE_BIT | ICC_SRE_ENB_BIT); diff --git a/src/arch/armv8/gicv2.c b/src/arch/armv8/gicv2.c index 69c2e862..2af82214 100644 --- a/src/arch/armv8/gicv2.c +++ b/src/arch/armv8/gicv2.c @@ -28,7 +28,7 @@ size_t gich_num_lrs() return ((gich->VTR & GICH_VTR_MSK) >> GICH_VTR_OFF) + 1; } -static inline void gicc_init() +static inline void gicc_init(void) { for (size_t i = 0; i < gich_num_lrs(); i++) { gich->LR[i] = 0; diff --git a/src/arch/armv8/gicv3.c b/src/arch/armv8/gicv3.c index bdf44d04..37a87fe6 100644 --- a/src/arch/armv8/gicv3.c +++ b/src/arch/armv8/gicv3.c @@ -25,7 +25,7 @@ size_t gich_num_lrs(void) return ((sysreg_ich_vtr_el2_read() & ICH_VTR_MSK) >> ICH_VTR_OFF) + 1; } -static inline void gicc_init() +static inline void gicc_init(void) { for (size_t i = 0; i < gich_num_lrs(); i++) { gich_write_lr(i, 0); @@ -38,7 +38,7 @@ static inline void gicc_init() sysreg_icc_igrpen1_el1_write(ICC_IGRPEN_EL1_ENB_BIT); } -static inline void gicr_init() +static inline void gicr_init(void) { gicr[cpu()->id].WAKER &= ~GICR_WAKER_ProcessorSleep_BIT; while (gicr[cpu()->id].WAKER & GICR_WAKER_ChildrenASleep_BIT) { } diff --git a/src/arch/armv8/inc/arch/fences.h b/src/arch/armv8/inc/arch/fences.h index 79239924..d3d1daf4 100644 --- a/src/arch/armv8/inc/arch/fences.h +++ b/src/arch/armv8/inc/arch/fences.h @@ -14,32 +14,32 @@ #define ISB() __asm__ volatile("isb\n\t" ::: "memory") -static inline void fence_ord_write() +static inline void fence_ord_write(void) { DMB(ishst); } -static inline void fence_ord_read() +static inline void fence_ord_read(void) { DMB(ishld); } -static inline void fence_ord() +static inline void fence_ord(void) { DMB(ish); } -static inline void fence_sync_write() +static inline void fence_sync_write(void) { DSB(ishst); } -static inline void fence_sync_read() +static inline void fence_sync_read(void) { DSB(ishld); } -static inline void fence_sync() +static inline void fence_sync(void) { DSB(ish); } diff --git a/src/arch/armv8/inc/arch/gic.h b/src/arch/armv8/inc/arch/gic.h index 83423846..65813c86 100644 --- a/src/arch/armv8/inc/arch/gic.h +++ b/src/arch/armv8/inc/arch/gic.h @@ -436,7 +436,7 @@ extern volatile struct gicr_hw* gicr; size_t gich_num_lrs(void); -static inline size_t gic_num_irqs() +static inline size_t gic_num_irqs(void) { size_t itlinenumber = bit32_extract(gicd->TYPER, GICD_TYPER_ITLN_OFF, GICD_TYPER_ITLN_LEN); return 32 * (itlinenumber + 1); diff --git a/src/arch/armv8/inc/arch/gicv2.h b/src/arch/armv8/inc/arch/gicv2.h index a1e6a85d..2eb7a209 100644 --- a/src/arch/armv8/inc/arch/gicv2.h +++ b/src/arch/armv8/inc/arch/gicv2.h @@ -26,7 +26,7 @@ static inline void gich_write_lr(size_t i, uint64_t val) } } -static inline uint32_t gich_get_hcr() +static inline uint32_t gich_get_hcr(void) { return gich->HCR; } @@ -36,12 +36,12 @@ static inline void gich_set_hcr(uint32_t hcr) gich->HCR = hcr; } -static inline uint32_t gich_get_misr() +static inline uint32_t gich_get_misr(void) { return gich->MISR; } -static inline uint64_t gich_get_eisr() +static inline uint64_t gich_get_eisr(void) { uint64_t eisr = gich->EISR[0]; if (NUM_LRS > 32) { @@ -50,7 +50,7 @@ static inline uint64_t gich_get_eisr() return eisr; } -static inline uint64_t gich_get_elrsr() +static inline uint64_t gich_get_elrsr(void) { uint64_t elsr = gich->ELSR[0]; if (NUM_LRS > 32) { @@ -59,7 +59,7 @@ static inline uint64_t gich_get_elrsr() return elsr; } -static inline uint32_t gicc_iar() +static inline uint32_t gicc_iar(void) { return gicc->IAR; } diff --git a/src/arch/armv8/inc/arch/gicv3.h b/src/arch/armv8/inc/arch/gicv3.h index 25812cc9..1a86a1df 100644 --- a/src/arch/armv8/inc/arch/gicv3.h +++ b/src/arch/armv8/inc/arch/gicv3.h @@ -112,7 +112,7 @@ static inline void gich_write_lr(size_t i, uint64_t val) } } -static inline uint32_t gich_get_hcr() +static inline uint32_t gich_get_hcr(void) { return (uint32_t)sysreg_ich_hcr_el2_read(); } @@ -122,22 +122,22 @@ static inline void gich_set_hcr(uint32_t hcr) sysreg_ich_hcr_el2_write(hcr); } -static inline uint32_t gich_get_misr() +static inline uint32_t gich_get_misr(void) { return (uint32_t)sysreg_ich_misr_el2_read(); } -static inline uint64_t gich_get_eisr() +static inline uint64_t gich_get_eisr(void) { return sysreg_ich_eisr_el2_read(); } -static inline uint64_t gich_get_elrsr() +static inline uint64_t gich_get_elrsr(void) { return sysreg_ich_elrsr_el2_read(); } -static inline uint32_t gicc_iar() +static inline uint32_t gicc_iar(void) { return (uint32_t)sysreg_icc_iar1_el1_read(); } diff --git a/src/arch/armv8/inc/arch/vm.h b/src/arch/armv8/inc/arch/vm.h index bbd18b7a..7e63986e 100644 --- a/src/arch/armv8/inc/arch/vm.h +++ b/src/arch/armv8/inc/arch/vm.h @@ -54,7 +54,7 @@ struct vcpu_arch { }; struct vcpu* vm_get_vcpu_by_mpidr(struct vm* vm, unsigned long mpidr); -void vcpu_arch_entry(); +void vcpu_arch_entry(void); bool vcpu_arch_profile_on(struct vcpu* vcpu); void vcpu_arch_profile_init(struct vcpu* vcpu, struct vm* vm); diff --git a/src/arch/riscv/asm_defs.c b/src/arch/riscv/asm_defs.c index 2259e264..6858f746 100644 --- a/src/arch/riscv/asm_defs.c +++ b/src/arch/riscv/asm_defs.c @@ -8,7 +8,7 @@ #include #include -__attribute__((used)) static void cpu_defines() +__attribute__((used)) static void cpu_defines(void) { DEFINE_SIZE(CPU_SIZE, struct cpu); @@ -18,7 +18,7 @@ __attribute__((used)) static void cpu_defines() DEFINE_OFFSET(CPU_VCPU_OFF, struct cpu, vcpu); } -__attribute__((used)) static void vcpu_defines() +__attribute__((used)) static void vcpu_defines(void) { DEFINE_SIZE(VCPU_ARCH_SIZE, struct vcpu_arch); DEFINE_OFFSET(VCPU_REGS_OFF, struct vcpu, regs); diff --git a/src/arch/riscv/inc/arch/cpu.h b/src/arch/riscv/inc/arch/cpu.h index 3a5ca07c..78b23451 100644 --- a/src/arch/riscv/inc/arch/cpu.h +++ b/src/arch/riscv/inc/arch/cpu.h @@ -17,7 +17,7 @@ struct cpu_arch { unsigned plic_cntxt; }; -static inline struct cpu* cpu() +static inline struct cpu* cpu(void) { return (struct cpu*)BAO_CPU_BASE; } diff --git a/src/arch/riscv/inc/arch/fences.h b/src/arch/riscv/inc/arch/fences.h index e5d8097a..d82d8565 100644 --- a/src/arch/riscv/inc/arch/fences.h +++ b/src/arch/riscv/inc/arch/fences.h @@ -5,32 +5,32 @@ #ifndef __FENCES_ARCH_H__ #define __FENCES_ARCH_H__ -static inline void fence_ord_write() +static inline void fence_ord_write(void) { __asm__ volatile("fence w, rw\n\t" ::: "memory"); } -static inline void fence_ord_read() +static inline void fence_ord_read(void) { __asm__ volatile("fence r, rw\n\t" ::: "memory"); } -static inline void fence_ord() +static inline void fence_ord(void) { __asm__ volatile("fence rw, rw\n\t" ::: "memory"); } -static inline void fence_sync_write() +static inline void fence_sync_write(void) { __asm__ volatile("fence ow, iorw\n\t" ::: "memory"); } -static inline void fence_sync_read() +static inline void fence_sync_read(void) { __asm__ volatile("fence ir, iorw\n\t" ::: "memory"); } -static inline void fence_sync() +static inline void fence_sync(void) { __asm__ volatile("fence iorw, iorw\n\t" ::: "memory"); } diff --git a/src/arch/riscv/inc/arch/tlb.h b/src/arch/riscv/inc/arch/tlb.h index 21ba3972..1e50cfbd 100644 --- a/src/arch/riscv/inc/arch/tlb.h +++ b/src/arch/riscv/inc/arch/tlb.h @@ -19,7 +19,7 @@ static inline void tlb_hyp_inv_va(vaddr_t va) sbi_remote_sfence_vma((1U << platform.cpu_num) - 1, 0, (unsigned long)va, PAGE_SIZE); } -static inline void tlb_hyp_inv_all() +static inline void tlb_hyp_inv_all(void) { sbi_remote_sfence_vma((1U << platform.cpu_num) - 1, 0, 0, 0); } diff --git a/src/arch/riscv/inc/arch/vm.h b/src/arch/riscv/inc/arch/vm.h index 3c1d63ec..cabb0b89 100644 --- a/src/arch/riscv/inc/arch/vm.h +++ b/src/arch/riscv/inc/arch/vm.h @@ -125,7 +125,7 @@ struct arch_regs { } __attribute__((__packed__, aligned(sizeof(unsigned long)))); -void vcpu_arch_entry(); +void vcpu_arch_entry(void); static inline void vcpu_arch_inject_hw_irq(struct vcpu* vcpu, irqid_t id) { diff --git a/src/arch/riscv/irqc/aia/inc/irqc.h b/src/arch/riscv/irqc/aia/inc/irqc.h index adbb5f0f..edf84658 100644 --- a/src/arch/riscv/irqc/aia/inc/irqc.h +++ b/src/arch/riscv/irqc/aia/inc/irqc.h @@ -19,12 +19,12 @@ #define HYP_IRQ_SM_INACTIVE APLIC_SOURCECFG_SM_INACTIVE #define HYP_IRQ_PRIO APLIC_TARGET_MAX_PRIO -static inline void irqc_init() +static inline void irqc_init(void) { aplic_init(); } -static inline void irqc_cpu_init() +static inline void irqc_cpu_init(void) { aplic_idc_init(); } @@ -41,7 +41,7 @@ static inline void irqc_config_irq(irqid_t int_id, bool en) } } -static inline void irqc_handle() +static inline void irqc_handle(void) { aplic_handle(); } diff --git a/src/arch/riscv/irqc/plic/inc/irqc.h b/src/arch/riscv/irqc/plic/inc/irqc.h index d0e3ccc2..ab6c0d4d 100644 --- a/src/arch/riscv/irqc/plic/inc/irqc.h +++ b/src/arch/riscv/irqc/plic/inc/irqc.h @@ -16,12 +16,12 @@ #define HART_REG_OFF PLIC_THRESHOLD_OFF #define IRQC_HART_INST PLIC_PLAT_CNTXT_NUM -static inline void irqc_init() +static inline void irqc_init(void) { plic_init(); } -static inline void irqc_cpu_init() +static inline void irqc_cpu_init(void) { plic_cpu_init(); } @@ -32,7 +32,7 @@ static inline void irqc_config_irq(irqid_t int_id, bool en) plic_set_prio(int_id, 0xFE); } -static inline void irqc_handle() +static inline void irqc_handle(void) { plic_handle(); } diff --git a/src/arch/riscv/irqc/plic/plic.c b/src/arch/riscv/irqc/plic/plic.c index 08b45c88..795f91fe 100644 --- a/src/arch/riscv/irqc/plic/plic.c +++ b/src/arch/riscv/irqc/plic/plic.c @@ -14,7 +14,7 @@ volatile struct plic_global_hw* plic_global; volatile struct plic_hart_hw* plic_hart; -static size_t plic_scan_max_int() +static size_t plic_scan_max_int(void) { size_t res = 0; for (size_t i = 1; i < PLIC_MAX_INTERRUPTS; i++) { diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 10888002..f75a755d 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -216,7 +216,7 @@ static struct sbiret sbi_time_handler(unsigned long fid) return (struct sbiret){ SBI_SUCCESS }; } -static void sbi_timer_irq_handler() +static void sbi_timer_irq_handler(void) { csrs_hvip_set(HIP_VSTIP); csrs_sie_clear(SIE_STIE); @@ -315,7 +315,7 @@ static struct sbiret sbi_rfence_handler(unsigned long fid) return ret; } -static struct sbiret sbi_hsm_start_handler() +static struct sbiret sbi_hsm_start_handler(void) { struct sbiret ret; vcpuid_t vhart_id = vcpu_readreg(cpu()->vcpu, REG_A0); @@ -357,7 +357,7 @@ static struct sbiret sbi_hsm_start_handler() return ret; } -static struct sbiret sbi_hsm_status_handler() +static struct sbiret sbi_hsm_status_handler(void) { struct sbiret ret; vcpuid_t vhart_id = vcpu_readreg(cpu()->vcpu, REG_A0); @@ -453,7 +453,7 @@ void sbi_init() } } - if (!interrupts_reserve(TIMR_INT_ID, sbi_timer_irq_handler)) { + if (!interrupts_reserve(TIMR_INT_ID, (irq_handler_t)sbi_timer_irq_handler)) { ERROR("Failed to reserve SBI TIMR_INT_ID interrupt"); } } diff --git a/src/arch/riscv/sync_exceptions.c b/src/arch/riscv/sync_exceptions.c index cf3e1d2e..e44c5414 100644 --- a/src/arch/riscv/sync_exceptions.c +++ b/src/arch/riscv/sync_exceptions.c @@ -41,9 +41,9 @@ static uint32_t read_ins(uintptr_t ins_addr) return ins; } -typedef size_t (*sync_handler_t)(); +typedef size_t (*sync_handler_t)(void); -extern size_t sbi_vs_handler(); +extern size_t sbi_vs_handler(void); static inline bool ins_ldst_decode(vaddr_t ins, struct emul_access* emul) { @@ -78,7 +78,7 @@ static inline bool is_pseudo_ins(uint32_t ins) return ins == TINST_PSEUDO_STORE || ins == TINST_PSEUDO_LOAD; } -static size_t guest_page_fault_handler() +static size_t guest_page_fault_handler(void) { vaddr_t addr = csrs_htval_read() << 2; diff --git a/src/core/inc/interrupts.h b/src/core/inc/interrupts.h index a48efc52..b0e389be 100644 --- a/src/core/inc/interrupts.h +++ b/src/core/inc/interrupts.h @@ -15,7 +15,7 @@ struct vm; typedef void (*irq_handler_t)(irqid_t int_id); -void interrupts_init(); +void interrupts_init(void); bool interrupts_reserve(irqid_t int_id, irq_handler_t handler); void interrupts_cpu_sendipi(cpuid_t target_cpu, irqid_t ipi_id); diff --git a/src/core/interrupts.c b/src/core/interrupts.c index b3440f7b..336cacc2 100644 --- a/src/core/interrupts.c +++ b/src/core/interrupts.c @@ -36,7 +36,7 @@ inline void interrupts_clear(irqid_t int_id) interrupts_arch_clear(int_id); } -inline void interrupts_init() +inline void interrupts_init(void) { interrupts_arch_init(); diff --git a/src/core/mpu/mem.c b/src/core/mpu/mem.c index 0b3fd10c..29b910e0 100644 --- a/src/core/mpu/mem.c +++ b/src/core/mpu/mem.c @@ -125,7 +125,7 @@ static inline priv_t as_priv(struct addr_space* as) return priv; } -static void as_init_boot_regions() +static void as_init_boot_regions(void) { /** * Add hypervisor mpu entries set up during boot to the vmpu: diff --git a/src/core/shmem.c b/src/core/shmem.c index b89a9688..b3cdb19d 100644 --- a/src/core/shmem.c +++ b/src/core/shmem.c @@ -9,7 +9,7 @@ static size_t shmem_table_size; static struct shmem* shmem_table; -static void shmem_alloc() +static void shmem_alloc(void) { for (size_t i = 0; i < shmem_table_size; i++) { struct shmem* shmem = &shmem_table[i]; From 420eb76b48ac67cff0355e50a817abd524859816 Mon Sep 17 00:00:00 2001 From: Miguel Silva Date: Wed, 24 Jul 2024 14:00:09 +0100 Subject: [PATCH 7/8] ref(fallthrough): Change the fallthrough annotation to attribute Clang compiler only accepts fallthrough annotation to be done using attribute(fallthrough). This is can be enforced in gcc using the flag -Wimplicit-fallthrough=5 Signed-off-by: Miguel Silva --- src/lib/printk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/printk.c b/src/lib/printk.c index e62fafa0..44292e01 100644 --- a/src/lib/printk.c +++ b/src/lib/printk.c @@ -123,10 +123,10 @@ size_t vsnprintk(char* buf, size_t buf_size, const char** fmt, va_list* args) case 'x': case 'X': flags = flags | F_BASE16; - /* fallthrough */ + __attribute__((fallthrough)); case 'u': flags = flags | F_UNSIGNED; - /* fallthrough */ + __attribute__((fallthrough)); case 'd': case 'i': va_copy(args_tmp, *args); From 4d6081e790b308629e7ebec000b7d44a46f05959 Mon Sep 17 00:00:00 2001 From: Miguel Silva Date: Wed, 24 Jul 2024 14:31:37 +0100 Subject: [PATCH 8/8] fix(inline): Fix inline functions Both MISRA and clang compiler force inline functions to be static. Functions that are used in multiple sources stop being inline because they cannot be static. The other inline functions become static and their prototype is removed from the header Signed-off-by: Miguel Silva --- src/arch/armv8/armv8-a/inc/arch/smmuv2.h | 4 ---- src/arch/armv8/armv8-a/iommu.c | 2 +- src/arch/armv8/armv8-a/smmuv2.c | 8 ++++---- src/arch/armv8/interrupts.c | 2 +- src/arch/armv8/vgic.c | 2 +- src/arch/riscv/interrupts.c | 2 +- src/arch/riscv/iommu.c | 2 +- src/core/interrupts.c | 10 +++++----- 8 files changed, 14 insertions(+), 18 deletions(-) diff --git a/src/arch/armv8/armv8-a/inc/arch/smmuv2.h b/src/arch/armv8/armv8-a/inc/arch/smmuv2.h index 6f158a00..cf96bb59 100644 --- a/src/arch/armv8/armv8-a/inc/arch/smmuv2.h +++ b/src/arch/armv8/armv8-a/inc/arch/smmuv2.h @@ -380,10 +380,6 @@ ssize_t smmu_alloc_sme(void); void smmu_write_ctxbnk(size_t ctx_id, paddr_t root_pt, asid_t vm_id); void smmu_write_sme(size_t sme, streamid_t mask, streamid_t id, bool group); void smmu_write_s2c(size_t sme, size_t ctx_id); -size_t smmu_sme_get_ctx(size_t sme); -streamid_t smmu_sme_get_id(size_t sme); -streamid_t smmu_sme_get_mask(size_t sme); -bool smmu_sme_is_group(size_t sme); bool smmu_compatible_sme_exists(streamid_t mask, streamid_t id, size_t ctx, bool group); #endif diff --git a/src/arch/armv8/armv8-a/iommu.c b/src/arch/armv8/armv8-a/iommu.c index 5c89fdc0..f9273223 100644 --- a/src/arch/armv8/armv8-a/iommu.c +++ b/src/arch/armv8/armv8-a/iommu.c @@ -64,7 +64,7 @@ static bool iommu_vm_arch_add(struct vm* vm, streamid_t mask, streamid_t id) return true; } -inline bool iommu_arch_vm_add_device(struct vm* vm, streamid_t id) +bool iommu_arch_vm_add_device(struct vm* vm, streamid_t id) { return iommu_vm_arch_add(vm, 0, id); } diff --git a/src/arch/armv8/armv8-a/smmuv2.c b/src/arch/armv8/armv8-a/smmuv2.c index e942577f..9e6734d6 100644 --- a/src/arch/armv8/armv8-a/smmuv2.c +++ b/src/arch/armv8/armv8-a/smmuv2.c @@ -52,22 +52,22 @@ struct smmu_priv smmu; /** * Accessors inline functions. */ -inline bool smmu_sme_is_group(size_t sme) +static inline bool smmu_sme_is_group(size_t sme) { return bitmap_get(smmu.grp_bitmap, sme); } -inline size_t smmu_sme_get_ctx(size_t sme) +static inline size_t smmu_sme_get_ctx(size_t sme) { return S2CR_CBNDX(smmu.hw.glbl_rs0->S2CR[sme]); } -inline streamid_t smmu_sme_get_id(size_t sme) +static inline streamid_t smmu_sme_get_id(size_t sme) { return SMMU_SMR_ID(smmu.hw.glbl_rs0->SMR[sme]); } -inline streamid_t smmu_sme_get_mask(size_t sme) +static inline streamid_t smmu_sme_get_mask(size_t sme) { return SMMU_SMR_MASK(smmu.hw.glbl_rs0->SMR[sme]); } diff --git a/src/arch/armv8/interrupts.c b/src/arch/armv8/interrupts.c index 049e741f..9d332e32 100644 --- a/src/arch/armv8/interrupts.c +++ b/src/arch/armv8/interrupts.c @@ -46,7 +46,7 @@ bool interrupts_arch_check(irqid_t int_id) return gic_get_pend(int_id); } -inline bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id) +bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id) { return (bitmap_get(interrupt_bitmap, int_id) && int_id > GIC_CPU_PRIV); } diff --git a/src/arch/armv8/vgic.c b/src/arch/armv8/vgic.c index 3f362da1..deeb97da 100644 --- a/src/arch/armv8/vgic.c +++ b/src/arch/armv8/vgic.c @@ -44,7 +44,7 @@ extern volatile const size_t VGIC_IPI_ID; void vgic_ipi_handler(uint32_t event, uint64_t data); CPU_MSG_HANDLER(vgic_ipi_handler, VGIC_IPI_ID) -inline struct vgic_int* vgic_get_int(struct vcpu* vcpu, irqid_t int_id, vcpuid_t vgicr_id) +struct vgic_int* vgic_get_int(struct vcpu* vcpu, irqid_t int_id, vcpuid_t vgicr_id) { if (int_id < GIC_CPU_PRIV) { struct vcpu* target_vcpu = vgicr_id == vcpu->id ? vcpu : vm_get_vcpu(vcpu->vm, vgicr_id); diff --git a/src/arch/riscv/interrupts.c b/src/arch/riscv/interrupts.c index 05bab96d..05bf7ad3 100644 --- a/src/arch/riscv/interrupts.c +++ b/src/arch/riscv/interrupts.c @@ -119,7 +119,7 @@ void interrupts_arch_clear(irqid_t int_id) } } -inline bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id) +bool interrupts_arch_conflict(bitmap_t* interrupt_bitmap, irqid_t int_id) { return bitmap_get(interrupt_bitmap, int_id); } diff --git a/src/arch/riscv/iommu.c b/src/arch/riscv/iommu.c index 65b62f60..2b77d93d 100644 --- a/src/arch/riscv/iommu.c +++ b/src/arch/riscv/iommu.c @@ -426,7 +426,7 @@ static bool iommu_vm_arch_add(struct vm* vm, deviceid_t dev_id) * * @returns true on success, false on error. */ -inline bool iommu_arch_vm_add_device(struct vm* vm, deviceid_t dev_id) +bool iommu_arch_vm_add_device(struct vm* vm, deviceid_t dev_id) { return iommu_vm_arch_add(vm, dev_id); } diff --git a/src/core/interrupts.c b/src/core/interrupts.c index 336cacc2..3ee9e972 100644 --- a/src/core/interrupts.c +++ b/src/core/interrupts.c @@ -16,27 +16,27 @@ spinlock_t irq_reserve_lock = SPINLOCK_INITVAL; irq_handler_t interrupt_handlers[MAX_INTERRUPTS]; -inline void interrupts_cpu_sendipi(cpuid_t target_cpu, irqid_t ipi_id) +void interrupts_cpu_sendipi(cpuid_t target_cpu, irqid_t ipi_id) { interrupts_arch_ipi_send(target_cpu, ipi_id); } -inline void interrupts_cpu_enable(irqid_t int_id, bool en) +void interrupts_cpu_enable(irqid_t int_id, bool en) { interrupts_arch_enable(int_id, en); } -inline bool interrupts_check(irqid_t int_id) +bool interrupts_check(irqid_t int_id) { return interrupts_arch_check(int_id); } -inline void interrupts_clear(irqid_t int_id) +void interrupts_clear(irqid_t int_id) { interrupts_arch_clear(int_id); } -inline void interrupts_init(void) +void interrupts_init(void) { interrupts_arch_init();