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Add fetch unit schematics.
Update to instruction memory access.
Took out reading/writing to/from instruction memory since this
is never used in the implemented backend. Cleaned up some of
the module interfaces by removing the unneeded pins. This
also simplifies the fetch unit quite a bit.
Adds information about simulating the processor in ModelSim
and how to simulate programs.
Add example program.
Add hex_converter program.
Add java class files to gitignore.
Add verilog files.