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Commits on Dec 5, 2012
  1. Add fetch unit schematics.

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  2. Update to instruction memory access.

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    Took out reading/writing to/from instruction memory since this
    is never used in the implemented backend. Cleaned up some of
    the module interfaces by removing the unneeded pins. This
    also simplifies the fetch unit quite a bit.
  3. Update README

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    Adds information about simulating the processor in ModelSim
    and how to simulate programs.
  4. Add example program.

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  5. Add hex_converter program.

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  6. Update README.

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  7. Add verilog files.

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  8. Initial commit.

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