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A processor for the BCAA ISA written in SystemVerilog.

branch: master
README.md

BCAA Processor

A processor implemented in SystemVerilog that conforms to the BCAA ISA. The processor is fully synthesizable in Quartus II and can be simulated in ModelSim for Altera.

Quartus II

The processor can be synthesized in Quartus II with the following settings:

  • Device Family: Cyclone II
  • Device: EP2C35F672C6
  • Top Level Entity: core
  • Simulation Tool: ModelSim-Altera (SystemVerilog)

Behavioral Simulation

The processor can be simulated using ModelSim for Altera. Included are two test benches, test.tfw and test_io.tfw.

  • test.tfw Runs the processor as normal, fetching and executing instructions from the instruction memory.
  • test_io.tfw Runs the processor with I/O devices specified in io_devices.v.

Timing Simulation

A timing simulation of the program can be accomplished by compiling core.svo in Quartus and launching a "Gate-Level Simulation" inside ModelSim. Be sure to comment out the following line in test-bench file of your choosing:

`define BEHAVIORAL

Simulating Programs

To simulate a program, you will have to use the assembler for the BCAA ISA to assemble a test program into a .coe file. You then must convert the .coe file into a .hex file that Altera tools will recognize, which can be done using the converter program included in hex_converter/.

Then, in ram_15_1024b.v, change the following line to reflect the location of your instruction memory .hex file:

`define THE_FILE_HEX "pushpop_i.hex"

Example Program

See the example/ directory for an example program that was assembled and converted to the .hex format.

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