H.264 Hardware Encoder in VHDL
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Project: hardh264

A hardware h264 video encoder written in VHDL suited to IP cameras and
megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is
using Xilinx tools and FPGAs but it is not specific to Xilinx.

Directory structure:
doc - documetation
src - vhdl source (synthesizable)
tests - test code and test vectors

Source code and other files are released here under a BSD-style licence

This is a mirror of the original project located at http://hardh264.sourceforge.net/