From 31a1e5696a5862aaeb474c937d28e84489383144 Mon Sep 17 00:00:00 2001 From: alfran Date: Thu, 16 Mar 2017 11:51:18 +0100 Subject: [PATCH 1/4] Updated library.properties --- library.properties | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/library.properties b/library.properties index b45ff73..f516f92 100644 --- a/library.properties +++ b/library.properties @@ -1,8 +1,14 @@ name=AGFX -version=0.1 -author= -email= -sentence=StAr Arduino Graphics Library +version=1.0 +author=Arduino +maintainer=Arduino +sentence=Star Arduino Graphics Library +sentence=Enables Graphical capability for Arduino Star Otto. +paragraph=The Arduino Graphics Library allows to use the STAR OTTO board the display on and create graphic effects or drawings. +category=Display +url=http://www.arduino.org/learning/reference/arduino-graphics + + paragraph=SGFX for stm32f4 url= architectures=stm32f4 From 49f4f1e4284d8a5ac5a791a2bcc7c101d5e35f45 Mon Sep 17 00:00:00 2001 From: alfran Date: Wed, 5 Apr 2017 13:30:40 +0200 Subject: [PATCH 2/4] library improvement and porting to new HAL core --- examples/agfx_test/agfx_test.ino | 23 ++++- library.properties | 5 +- src/agfx.cpp | 20 ++++ src/agfx.h | 6 +- src/ft6x06.c | 7 +- src/star_dsi.c | 171 ++++++++++++++++++++++++------- src/star_dsi.h | 6 +- src/star_sdram.c | 25 +++-- src/star_sdram.h | 1 - src/star_ts.c | 2 +- 10 files changed, 202 insertions(+), 64 deletions(-) diff --git a/examples/agfx_test/agfx_test.ino b/examples/agfx_test/agfx_test.ino index a15b676..28856d1 100644 --- a/examples/agfx_test/agfx_test.ino +++ b/examples/agfx_test/agfx_test.ino @@ -9,30 +9,47 @@ void setup() void loop() { + agfx.showScreen(0); + agfx.setDrawScreen(0); agfx.fill(AGFX_WHITE); + agfx.setDrawScreen(1); agfx.background(AGFX_WHITE); + agfx.showScreen(1); agfx.demoLine(2); delay(1000); + agfx.setDrawScreen(0); agfx.background(AGFX_WHITE); agfx.demoPolygon(); + agfx.showScreen(0); delay(2000); + agfx.setDrawScreen(1); agfx.background(AGFX_WHITE); agfx.demoCircle(); + agfx.showScreen(1); delay(2000); + agfx.setDrawScreen(0); agfx.background(AGFX_WHITE); agfx.demoEllipse(); + agfx.showScreen(0); delay(2000); - agfx.background(AGFX_WHITE); + // Copy shown screen to hidden screen and add some text + agfx.setDrawScreen(1); + agfx.copyScreen(0, 1); agfx.demoText(); + agfx.showScreen(1); delay(3000); - // Blocking demo + agfx.setDrawScreen(0); agfx.background(AGFX_WHITE); - agfx.demoTouch(); + agfx.showScreen(0); + + // Blocking demo + //agfx.background(AGFX_WHITE); + //agfx.demoTouch(); } diff --git a/library.properties b/library.properties index f516f92..3226af5 100644 --- a/library.properties +++ b/library.properties @@ -1,5 +1,5 @@ name=AGFX -version=1.0 +version=1.1 author=Arduino maintainer=Arduino sentence=Star Arduino Graphics Library @@ -8,7 +8,6 @@ paragraph=The Arduino Graphics Library allows to use the STAR OTTO board the dis category=Display url=http://www.arduino.org/learning/reference/arduino-graphics - -paragraph=SGFX for stm32f4 +paragraph=AGFX for stm32f4 url= architectures=stm32f4 diff --git a/src/agfx.cpp b/src/agfx.cpp index 4b18769..1c40f4f 100644 --- a/src/agfx.cpp +++ b/src/agfx.cpp @@ -71,6 +71,26 @@ bool AGFX::begin() return true; } +void AGFX::setDrawScreen(uint8_t scrIdx) +{ + STAR_DSI_SetDrawScreen(scrIdx); +} + +uint8_t AGFX::getDrawScreen(void) +{ + return STAR_DSI_GetDrawScreen(); +} + +void AGFX::showScreen(uint8_t scrIdx) +{ + STAR_DSI_ShowScreen(scrIdx); +} + +void AGFX::copyScreen(uint8_t fromScrIdx, uint8_t toScrIdx) +{ + STAR_DSI_CopyScreen(fromScrIdx, toScrIdx); +} + // Processing stype API ------------------- BEGIN -------------------- uint32_t AGFX::color(uint8_t r, uint8_t g, uint8_t b, uint8_t alpha) { diff --git a/src/agfx.h b/src/agfx.h index 1d26023..683d6db 100644 --- a/src/agfx.h +++ b/src/agfx.h @@ -4,6 +4,7 @@ #include #include "agfx_ll.h" #include "agfx_colors.h" +//#include "star_ts.h" #define ENABLE_DEMOS @@ -12,6 +13,10 @@ class AGFX public: AGFX(); bool begin(); + void setDrawScreen(uint8_t scrIdx); + uint8_t getDrawScreen(void); + void showScreen(uint8_t scrIdx); + void copyScreen(uint8_t fromScrIdx, uint8_t toScrIdx); uint32_t color(uint8_t r, uint8_t g, uint8_t b, uint8_t alpha); uint32_t color(uint8_t r, uint8_t g, uint8_t b); uint32_t color(uint8_t gray, uint8_t alpha); @@ -55,4 +60,3 @@ class AGFX }; #endif // _AGFX_H_INCLUDED - diff --git a/src/ft6x06.c b/src/ft6x06.c index 0e9995f..e54ec62 100644 --- a/src/ft6x06.c +++ b/src/ft6x06.c @@ -11,7 +11,7 @@ #define I2C_SCL_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() #define I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET() #define I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET() -#define I2C_SCL_SDA_GPIO_PORT HAL_GPIOB +#define I2C_SCL_SDA_GPIO_PORT GPIOB #define I2C_SCL_PIN GPIO_PIN_8 #define I2C_SCL_SDA_AF GPIO_AF4_I2C1 #define I2C_SDA_PIN GPIO_PIN_9 @@ -19,13 +19,13 @@ #define I2C_ER_IRQn I2C1_ER_IRQn #else // BOARD_DISCO469 #define I2C_SCL_FREQ_KHZ 400000 -#define I2C_INSTANCE HAL_I2C3 +#define I2C_INSTANCE I2C3 #define I2C_CLK_ENABLE() __HAL_RCC_I2C3_CLK_ENABLE() #define DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE() #define I2C_SCL_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE() #define I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET() #define I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET() -#define I2C_SCL_SDA_GPIO_PORT HAL_GPIOH +#define I2C_SCL_SDA_GPIO_PORT GPIOH #define I2C_SCL_PIN GPIO_PIN_7 #define I2C_SDA_PIN GPIO_PIN_8 #define I2C_SCL_SDA_AF GPIO_AF4_I2C3 @@ -592,4 +592,3 @@ static uint8_t ft6x06_GetInstance(uint16_t DeviceAddr) return 0xFF; } - diff --git a/src/star_dsi.c b/src/star_dsi.c index df29e99..ace2f88 100644 --- a/src/star_dsi.c +++ b/src/star_dsi.c @@ -1,26 +1,35 @@ #include "star_dsi.h" #include "stm32f469xx.h" -// TODO -//#define ENABLE_IRQ - +#define ENABLE_LTDC_IRQ +// Not used yet +//#define ENABLE_DMA2D_IRQ +//#define ENABLE_DSI_IRQ // alfran: DMA2D_Color_Mode DMA2D Color Mode #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */ -#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */ -#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */ -#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */ -#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */ - - +//#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */ +//#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */ +//#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */ +//#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */ + +// Valid only for 800x480 32bpp +#define SCR_SIZE ((uint32_t)0x00180000) // slightly larger than 800*480*4 +#define MAX_SCR_COUNT 2 #define BG_LAYER_ADDR ((uint32_t)0xC0000000) -//#define NUM_LAYERS ((uint32_t)2) #define BG_LAYER_IDX ((uint32_t)0) -#define FG_LAYER_IDX ((uint32_t)1) +//#define FG_LAYER_IDX ((uint32_t)1) +//#define NUM_LAYERS ((uint32_t)2) #define LCD_OTM8009A_ID ((uint32_t)0) -#define FB_ADDR(_x, _y) \ - (hltdc.LayerCfg[currLayer].FBStartAdress + 4*(panelWidth*(_y)+(_x))) +#define FB_ADDR(_currScrIdx,_x, _y) \ + (hltdc.LayerCfg[currLayer].FBStartAdress \ + + _currScrIdx*SCR_SIZE \ + + 4*(panelWidth*(_y)+(_x))) +#define MIN(_a, _b) ( (_a) > (_b) ? (_b) : (_a) ) +#define DMA2D_MAX_SIZE 128U +#define DMA2D_MAX_AREA (DMA2D_MAX_SIZE*DMA2D_MAX_SIZE) +#define IS_VBLANK() (LTDC->CDSR & LTDC_CDSR_VSYNCS) // #ifdef BOARD_DISCO469 // #define RES_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE() @@ -28,11 +37,13 @@ // #define GPIO_RES_PIN GPIO_PIN_7 // #else #define RES_GPIO_CLK_ENABLE() __HAL_RCC_GPIOK_CLK_ENABLE() - #define GPIO_RES_PORT HAL_GPIOK + #define GPIO_RES_PORT GPIOK #define GPIO_RES_PIN GPIO_PIN_7 //#endif -static uint32_t currLayer = BG_LAYER_IDX; +static uint32_t currLayer = BG_LAYER_IDX; +static uint32_t currScrIdx = 0; +static volatile uint8_t swapScrBuf = 0; static DSI_VidCfgTypeDef hdsivid; static DMA2D_HandleTypeDef hdma2d; static LTDC_HandleTypeDef hltdc; @@ -73,40 +84,69 @@ static void LowLevelInit(void) __HAL_RCC_DSI_FORCE_RESET(); __HAL_RCC_DSI_RELEASE_RESET(); -#ifdef ENABLE_IRQ - //* @brief NVIC configuration for LTDC interrupt that is now enabled +#ifdef ENABLE_LTDC_IRQ + // NVIC configuration for LTDC HAL_NVIC_SetPriority(LTDC_IRQn, 3, 0); HAL_NVIC_EnableIRQ(LTDC_IRQn); +#endif - //* @brief NVIC configuration for DMA2D interrupt that is now enabled +#ifdef ENABLE_DMA2D_IRQ + // NVIC configuration for DMA2D HAL_NVIC_SetPriority(DMA2D_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA2D_IRQn); +#endif - //* @brief NVIC configuration for DSI interrupt that is now enabled +#ifdef ENABLE_DSI_IRQ + // NVIC configuration for DSI HAL_NVIC_SetPriority(DSI_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DSI_IRQn); #endif } -#ifdef ENABLE_IRQ -void STAR_DSI_DMA2D_IRQHandler(void) +#ifdef ENABLE_LTDC_IRQ +void __irq_LTDC_IRQHandler(void) { - HAL_DMA2D_IRQHandler(&hdma2d); + HAL_LTDC_IRQHandler(&hltdc); +} + +void __irq_LTDC_ER_IRQHandler(void) +{ + HAL_LTDC_IRQHandler(&hltdc); +} + +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + static uint32_t cnt = 0; + + if (swapScrBuf) { + uint32_t addr = hltdc->LayerCfg[currLayer].FBStartAdress; + addr += currScrIdx * SCR_SIZE; + LTDC_LAYER(hltdc, currLayer)->CFBAR = addr; + __HAL_LTDC_RELOAD_CONFIG(hltdc); + swapScrBuf = 0; + } + + HAL_LTDC_ProgramLineEvent(hltdc, 0); } -void STAR_DSI_DSI_IRQHandler(void) +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) { - HAL_DSI_IRQHandler(&(hdsi)); + // Re-enable FIFO underrun error IRQ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU); } +#endif -void STAR_DSI_LTDC_IRQHandler(void) +#ifdef ENABLE_DMA2D_IRQ +void __irq_DMA2D_IRQHandler(void) { - HAL_LTDC_IRQHandler(&(hltdc)); + HAL_DMA2D_IRQHandler(&hdma2d); } +#endif -void STAR_DSI_LTDC_ER_IRQHandler(void) +#ifdef ENABLE_DSI_IRQ +void __irq_DSI_IRQHandler(void) { - HAL_LTDC_IRQHandler(&(hltdc)); + HAL_DSI_IRQHandler(&hdsi); } #endif @@ -152,7 +192,7 @@ uint8_t STAR_DSI_Init(LCD_OrientationTypeDef orientation) LcdResetOnce(); LowLevelInit(); - hdsi.Instance = HAL_DSI; + hdsi.Instance = DSI; HAL_DSI_DeInit(&(hdsi)); dsiPllInit.PLLNDIV = 125; @@ -255,7 +295,7 @@ uint8_t STAR_DSI_Init(LCD_OrientationTypeDef orientation) hltdc.Init.Backcolor.Green = 255; hltdc.Init.Backcolor.Red = 255; hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; - hltdc.Instance = HAL_LTDC; + hltdc.Instance = LTDC; // Get LTDC Configuration from DSI Configuration HAL_LTDC_StructInitFromVideoConfig(&(hltdc), &(hdsivid)); @@ -267,6 +307,10 @@ uint8_t STAR_DSI_Init(LCD_OrientationTypeDef orientation) // Layer init LayerInit(BG_LAYER_IDX, BG_LAYER_ADDR); +#ifdef ENABLE_LTDC_IRQ + HAL_LTDC_ProgramLineEvent(&hltdc, 0); +#endif + return LCD_OK; } @@ -280,19 +324,50 @@ uint16_t STAR_DSI_PanelHeight(void) return panelHeight; } +void STAR_DSI_SetDrawScreen(uint8_t scrIdx) +{ + if (scrIdx < MAX_SCR_COUNT) + currScrIdx = scrIdx; +} + +uint8_t STAR_DSI_GetDrawScreen(void) +{ + return currScrIdx; +} + +void STAR_DSI_ShowScreen(uint8_t scrIdx) +{ + // Flip screen at next VSYNC + swapScrBuf = 1; + while (swapScrBuf) ; +} + +void STAR_DSI_CopyScreen(uint8_t fromIdx, uint8_t toIdx) +{ + uint32_t offset = 0; + + while (offset < SCR_SIZE) { + while (!IS_VBLANK()) ; + memcpy(FB_ADDR(toIdx, 0, 0)+offset, FB_ADDR(fromIdx, 0, 0)+offset, DMA2D_MAX_AREA); + offset += DMA2D_MAX_AREA; + } +} + void STAR_DSI_DrawPoint(uint16_t x, uint16_t y, uint32_t color) { - *(__IO uint32_t*)(hltdc.LayerCfg[currLayer].FBStartAdress + - 4*(y*panelWidth + x)) = color; + *(__IO uint32_t*)FB_ADDR(currScrIdx, x, y) = color; } -void STAR_DSI_FillBufferDma(uint32_t layerIdx, void *dst, uint32_t width, +static void STAR_DSI_FillBufferDma(uint32_t layerIdx, void *dst, uint32_t width, uint32_t height, uint32_t lineOffset, uint32_t color) { + // Wait for VBLANK start + while (!IS_VBLANK()) ; + hdma2d.Init.Mode = DMA2D_R2M; hdma2d.Init.ColorMode = DMA2D_ARGB8888; hdma2d.Init.OutputOffset = lineOffset; - hdma2d.Instance = HAL_DMA2D; + hdma2d.Instance = DMA2D; if (HAL_DMA2D_Init(&hdma2d) == HAL_OK) if (HAL_DMA2D_ConfigLayer(&hdma2d, layerIdx) == HAL_OK) @@ -304,8 +379,32 @@ void STAR_DSI_FillBufferDma(uint32_t layerIdx, void *dst, uint32_t width, void STAR_DSI_FillRectDma(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint32_t color) { - STAR_DSI_FillBufferDma(currLayer, FB_ADDR(x, y), width, height, - panelWidth - width, color); + uint16_t tx = x, ty = y; + uint16_t tw, th; + uint16_t rw = width, rh = height; // Width/height to go + + // If blitting area takes more than one VSYNC period, + // we split it in several calls + if (width*height > DMA2D_MAX_AREA) { + while (rh) { + th = MIN(DMA2D_MAX_SIZE, rh); + while (rw) { + tw = MIN(DMA2D_MAX_SIZE, rw); + STAR_DSI_FillBufferDma(currLayer, FB_ADDR(currScrIdx, tx, ty), tw, th, + panelWidth - tw, color); + tx += DMA2D_MAX_SIZE; + rw -= tw; + } + ty += DMA2D_MAX_SIZE; + rh -= th; + tx = x; + rw = width; + } + } + else { + STAR_DSI_FillBufferDma(currLayer, FB_ADDR(currScrIdx, x, y), width, height, + panelWidth - width, color); + } } void STAR_DSI_DisplayOn(void) diff --git a/src/star_dsi.h b/src/star_dsi.h index 64470ec..6fc8c70 100644 --- a/src/star_dsi.h +++ b/src/star_dsi.h @@ -29,9 +29,11 @@ extern void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams); extern uint8_t STAR_DSI_Init(LCD_OrientationTypeDef orientation); extern uint16_t STAR_DSI_PanelWidth(void); extern uint16_t STAR_DSI_PanelHeight(void); +extern void STAR_DSI_SetDrawScreen(uint8_t scrIdx); +extern uint8_t STAR_DSI_GetDrawScreen(void); +extern void STAR_DSI_ShowScreen(uint8_t scrIdx); +extern void STAR_DSI_CopyScreen(uint8_t fromIdx, uint8_t toIdx); extern void STAR_DSI_DrawPoint(uint16_t x, uint16_t y, uint32_t color); -extern void STAR_DSI_FillBufferDma(uint32_t layerIdx, void *dst, - uint32_t width, uint32_t height, uint32_t lineOffset, uint32_t color); extern void STAR_DSI_FillRectDma(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint32_t color); extern void STAR_DSI_DisplayOn(void); diff --git a/src/star_sdram.c b/src/star_sdram.c index 9741581..aa2e8a3 100644 --- a/src/star_sdram.c +++ b/src/star_sdram.c @@ -116,44 +116,44 @@ static void LowLevelInit(SDRAM_HandleTypeDef *hsdram) /* GPIOC configuration : PC0 is SDNWE */ gpio_init_structure.Pin = GPIO_PIN_0; - HAL_GPIO_Init(HAL_GPIOC, &gpio_init_structure); + HAL_GPIO_Init(GPIOC, &gpio_init_structure); /* GPIOD configuration */ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\ GPIO_PIN_14 | GPIO_PIN_15; - HAL_GPIO_Init(HAL_GPIOD, &gpio_init_structure); + HAL_GPIO_Init(GPIOD, &gpio_init_structure); /* GPIOE configuration */ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ GPIO_PIN_15; - HAL_GPIO_Init(HAL_GPIOE, &gpio_init_structure); + HAL_GPIO_Init(GPIOE, &gpio_init_structure); /* GPIOF configuration */ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ GPIO_PIN_15; - HAL_GPIO_Init(HAL_GPIOF, &gpio_init_structure); + HAL_GPIO_Init(GPIOF, &gpio_init_structure); /* GPIOG configuration */ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ GPIO_PIN_15; - HAL_GPIO_Init(HAL_GPIOG, &gpio_init_structure); + HAL_GPIO_Init(GPIOG, &gpio_init_structure); /* GPIOH configuration */ gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3; - HAL_GPIO_Init(HAL_GPIOH, &gpio_init_structure); + HAL_GPIO_Init(GPIOH, &gpio_init_structure); #ifdef SDRAM_32BIT_ACCESS /* GPIOH configuration */ gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\ GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; - HAL_GPIO_Init(HAL_GPIOH, &gpio_init_structure); + HAL_GPIO_Init(GPIOH, &gpio_init_structure); /* GPIOI configuration */ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10; - HAL_GPIO_Init(HAL_GPIOI, &gpio_init_structure); + HAL_GPIO_Init(GPIOI, &gpio_init_structure); #else #ifdef BOARD_DISCO469 // Force unused pins status in 16bit acces mode @@ -161,13 +161,13 @@ static void LowLevelInit(SDRAM_HandleTypeDef *hsdram) gpio_init_structure.Pull = GPIO_PULLUP; gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |\ GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10; - HAL_GPIO_Init(HAL_GPIOI, &gpio_init_structure); + HAL_GPIO_Init(GPIOI, &gpio_init_structure); gpio_init_structure.Pin = GPIO_PIN_4 | GPIO_PIN_5; gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; gpio_init_structure.Pull = GPIO_PULLDOWN; - HAL_GPIO_Init(HAL_GPIOI, &gpio_init_structure); - HAL_GPIO_WritePin(HAL_GPIOI, GPIO_PIN_4, 0); - HAL_GPIO_WritePin(HAL_GPIOI, GPIO_PIN_5, 0); + HAL_GPIO_Init(GPIOI, &gpio_init_structure); + HAL_GPIO_WritePin(GPIOI, GPIO_PIN_4, 0); + HAL_GPIO_WritePin(GPIOI, GPIO_PIN_5, 0); #endif // BOARD_DISCO469 #endif // SDRAM_32BIT_ACCESS @@ -271,4 +271,3 @@ uint8_t STAR_SDRAM_Test(void) return res; } - diff --git a/src/star_sdram.h b/src/star_sdram.h index f341379..9842dcb 100644 --- a/src/star_sdram.h +++ b/src/star_sdram.h @@ -20,4 +20,3 @@ extern uint8_t STAR_SDRAM_Test(void); #endif #endif // _STAR_SDRAM_H - diff --git a/src/star_ts.c b/src/star_ts.c index 6fab94d..adbd9c1 100644 --- a/src/star_ts.c +++ b/src/star_ts.c @@ -15,7 +15,7 @@ // #define TS_INT_IRQ_HANDLER __irq_exti9_5 // #else #define TS_INT_PIN ((uint32_t)GPIO_PIN_0) -#define TS_INT_GPIO_PORT ((GPIO_TypeDef*)HAL_GPIOI) +#define TS_INT_GPIO_PORT ((GPIO_TypeDef*)GPIOI) #define TS_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() #define TS_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() #define TS_INT_EXTI_IRQn EXTI0_IRQn From 9b955de671fd4ab014092c9bfdc0757125fdfe20 Mon Sep 17 00:00:00 2001 From: alfran Date: Thu, 6 Apr 2017 15:56:14 +0200 Subject: [PATCH 3/4] updating HAL device names --- src/star_dsi.c | 14 +++++++++----- src/star_sdram.h | 1 + src/star_ts.c | 2 +- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/star_dsi.c b/src/star_dsi.c index ace2f88..6e8bd39 100644 --- a/src/star_dsi.c +++ b/src/star_dsi.c @@ -33,7 +33,7 @@ // #ifdef BOARD_DISCO469 // #define RES_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE() -// #define GPIO_RES_PORT HAL_GPIOH +// #define GPIO_RES_PORT GPIOH // #define GPIO_RES_PIN GPIO_PIN_7 // #else #define RES_GPIO_CLK_ENABLE() __HAL_RCC_GPIOK_CLK_ENABLE() @@ -43,6 +43,7 @@ static uint32_t currLayer = BG_LAYER_IDX; static uint32_t currScrIdx = 0; +static uint32_t showScrIdx = 0; static volatile uint8_t swapScrBuf = 0; static DSI_VidCfgTypeDef hdsivid; static DMA2D_HandleTypeDef hdma2d; @@ -120,7 +121,7 @@ void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) if (swapScrBuf) { uint32_t addr = hltdc->LayerCfg[currLayer].FBStartAdress; - addr += currScrIdx * SCR_SIZE; + addr += showScrIdx * SCR_SIZE; LTDC_LAYER(hltdc, currLayer)->CFBAR = addr; __HAL_LTDC_RELOAD_CONFIG(hltdc); swapScrBuf = 0; @@ -337,9 +338,12 @@ uint8_t STAR_DSI_GetDrawScreen(void) void STAR_DSI_ShowScreen(uint8_t scrIdx) { - // Flip screen at next VSYNC - swapScrBuf = 1; - while (swapScrBuf) ; + // Change visbile screen at next VSYNC + if (scrIdx < MAX_SCR_COUNT) { + showScrIdx = scrIdx; + swapScrBuf = 1; + while (swapScrBuf) ; + } } void STAR_DSI_CopyScreen(uint8_t fromIdx, uint8_t toIdx) diff --git a/src/star_sdram.h b/src/star_sdram.h index 9842dcb..f341379 100644 --- a/src/star_sdram.h +++ b/src/star_sdram.h @@ -20,3 +20,4 @@ extern uint8_t STAR_SDRAM_Test(void); #endif #endif // _STAR_SDRAM_H + diff --git a/src/star_ts.c b/src/star_ts.c index adbd9c1..80f90d5 100644 --- a/src/star_ts.c +++ b/src/star_ts.c @@ -8,7 +8,7 @@ // #ifdef BOARD_DISCO469 // #define TS_INT_PIN ((uint32_t)GPIO_PIN_5) -// #define TS_INT_GPIO_PORT ((GPIO_TypeDef*)HAL_GPIOJ) +// #define TS_INT_GPIO_PORT ((GPIO_TypeDef*)GPIOJ) // #define TS_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOJ_CLK_ENABLE() // #define TS_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOJ_CLK_DISABLE() // #define TS_INT_EXTI_IRQn EXTI9_5_IRQn From 8fda823d2cb7ff4ea29c978889e481c90adaccf2 Mon Sep 17 00:00:00 2001 From: alfran Date: Wed, 26 Apr 2017 13:09:12 +0200 Subject: [PATCH 4/4] fix for HAL based Core --- src/stm32f4xx_hal_sdram.c | 853 ++++++++++++++++++++++++++++++++++++++ src/stm32f4xx_hal_sdram.h | 197 +++++++++ 2 files changed, 1050 insertions(+) create mode 100644 src/stm32f4xx_hal_sdram.c create mode 100644 src/stm32f4xx_hal_sdram.h diff --git a/src/stm32f4xx_hal_sdram.c b/src/stm32f4xx_hal_sdram.c new file mode 100644 index 0000000..eb2a006 --- /dev/null +++ b/src/stm32f4xx_hal_sdram.c @@ -0,0 +1,853 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_sdram.c + * @author MCD Application Team + * @version V1.6.0 + * @date 04-November-2016 + * @brief SDRAM HAL module driver. + * This file provides a generic firmware to drive SDRAM memories mounted + * as external device. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SDRAM memories. It uses the FMC layer functions to interface + with SDRAM devices. + The following sequence should be followed to configure the FMC to interface + with SDRAM memories: + + (#) Declare a SDRAM_HandleTypeDef handle structure, for example: + SDRAM_HandleTypeDef hdsram + + (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SDRAM device + + (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: + FMC_SDRAM_TimingTypeDef Timing; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() + (##) Control register configuration using the FMC SDRAM interface function + FMC_SDRAM_Init() + (##) Timing register configuration using the FMC SDRAM interface function + FMC_SDRAM_Timing_Init() + (##) Program the SDRAM external device by applying its initialization sequence + according to the device plugged in your hardware. This step is mandatory + for accessing the SDRAM device. + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the SDRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access + (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ + HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or + the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM + device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef + structure. + + (#) You can continuously monitor the SDRAM device HAL state by calling the function + HAL_SDRAM_GetState() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup SDRAM SDRAM + * @brief SDRAM driver modules + * @{ + */ +#ifdef HAL_SDRAM_MODULE_ENABLED +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### SDRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SDRAM device initialization sequence. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Timing: Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if(hsdram == NULL) + { + return HAL_ERROR; + } + + if(hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Initialize SDRAM control Interface */ + FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + + /* Initialize SDRAM timing Interface */ + FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform the SDRAM device initialization sequence. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspDeInit(hsdram); + + /* Configure the SDRAM registers with their reset values */ + FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + + /* Reset the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief SDRAM MSP Init. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SDRAM MSP DeInit. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function handles SDRAM refresh error interrupt request. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status +*/ +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) +{ + /* Check SDRAM interrupt Rising edge flag */ + if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + { + /* SDRAM refresh error interrupt callback */ + HAL_SDRAM_RefreshErrorCallback(hsdram); + + /* Clear SDRAM refresh error interrupt pending bit */ + __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); + } +} + +/** + * @brief SDRAM Refresh error callback. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma: DMA handle + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SDRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit data buffer from the SDRAM memory. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0U; BufferSize--) + { + *pDstBuffer = *(__IO uint8_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes 8-bit data buffer to SDRAM memory. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint32_t tmp = 0U; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0U; BufferSize--) + { + *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Reads 16-bit data buffer from the SDRAM memory. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0U; BufferSize--) + { + *pDstBuffer = *(__IO uint16_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes 16-bit data buffer to SDRAM memory. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; + uint32_t tmp = 0U; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0U; BufferSize--) + { + *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Reads 32-bit data buffer from the SDRAM memory. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0U; BufferSize--) + { + *pDstBuffer = *(__IO uint32_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes 32-bit data buffer to SDRAM memory. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + uint32_t tmp = 0U; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0U; BufferSize--) + { + *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SDRAM memory using DMA transfer. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + uint32_t tmp = 0U; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(tmp == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + uint32_t tmp = 0U; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SDRAM write protection. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Enable write protection */ + FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + + return HAL_OK; +} + +/** + * @brief Disables dynamically SDRAM write protection. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Disable write protection */ + FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Sends Command to the SDRAM bank. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Command: SDRAM command structure + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state */ + if(Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Programs the SDRAM Memory Refresh rate. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param RefreshRate: The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param AutoRefreshNumber: The SDRAM auto Refresh number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Set the Auto-Refresh number */ + FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Returns the SDRAM memory current mode. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval The SDRAM memory mode. + */ +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) +{ + /* Return the SDRAM memory current mode */ + return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SDRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SDRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SDRAM state. + * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL state + */ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +{ + return hsdram->State; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/stm32f4xx_hal_sdram.h b/src/stm32f4xx_hal_sdram.h new file mode 100644 index 0000000..538d400 --- /dev/null +++ b/src/stm32f4xx_hal_sdram.h @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_sdram.h + * @author MCD Application Team + * @version V1.6.0 + * @date 04-November-2016 + * @brief Header file of SDRAM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_SDRAM_H +#define __STM32F4xx_HAL_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_fmc.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Types SDRAM Exported Types + * @{ + */ + +/** + * @brief HAL SDRAM State structure definition + */ +typedef enum +{ + HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ + HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ + HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ + HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ + HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ + HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ + +}HAL_SDRAM_StateTypeDef; + +/** + * @brief SDRAM handle Structure definition + */ +typedef struct +{ + FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ + + __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ + + HAL_LockTypeDef Lock; /*!< SDRAM locking object */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +}SDRAM_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros + * @{ + */ + +/** @brief Reset SDRAM handle state + * @param __HANDLE__: specifies the SDRAM handle. + * @retval None + */ +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @addtogroup SDRAM_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions *********************************/ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); + +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); + +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group3 + * @{ + */ +/* SDRAM Control functions *****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group4 + * @{ + */ +/* SDRAM State functions ********************************************************/ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_SDRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/