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A compiler, assembler, and processor.
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assembler tuples Jun 15, 2017
common
compiler tuples Jun 15, 2017
emulator emulator, test bench updates, instruction logging Jun 29, 2017
processor branch debug, old code. pushing for helpfulness Dec 17, 2017
test_bench
.gitignore emulator, test bench updates, instruction logging Jun 29, 2017
README.md branch debug, old code. pushing for helpfulness Dec 17, 2017
install_depends include gtkwave Jul 8, 2017
makefile emulator, test bench updates, instruction logging Jun 29, 2017

README.md

This project is currently on pause because I have started graduate school
I am not sure if I will come back to it
The latest code are on branches ooo, ooo1, ooo2.

Compiler - Assembler - Processor

This repository implements a compiler, assembler and a processor.

Compiler

OCaml.
Most of code taken from Northeastern compilers course.
Compiles to x86.

Assembler

Ocaml.
Coverts x86 to a RISC ISA and assembles to binary.

Processor

Verilog.
Implements a RISC ISA capable of running all instructions generated by assembler.

Test Bench

C - Verilog Programming Interface.
Simulates instruction memory, data memory, and registers.
Runs through different types of tests:

  1. Binary tests - binary code. and checks to make sure main memory and registers are the same as expected
  2. Assembly Tests - x86 assembly code. tests only the final result in eax.
  3. Code Tests - abstract code. tests only the final result in eax.

Running the code

There is a dependency script that may or may not work for getting the dependencies.
Once these are acquired, the makefile can be run which will compile all four modules and run the test bench.

Future Features

  1. Super scalar 👍
  2. Performance metrics (branch misses, IPC, instruction histograms, stalls) 👍
  3. Branch predictor 👍
  4. Compiler - Tuples 👍
  5. Emulator 👍
  6. Instruction Logs 👍
  7. Out of order
  8. Memory simulator (cache / memory heirarchy with random latency)
  9. Combining instruction memory and data memory
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