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used gated clock instead of global 180 deg phased clock

adapted for arcade megawing
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1 parent 59d7dcb commit e1a614da30e71813fa0a4713955b2d32ea0924fb @ben0109 committed Oct 3, 2012
Showing with 584 additions and 615 deletions.
  1. +4 −18 clock.vhd
  2. BIN final.bit
  3. +0 −1 full_pipeline.vhd
  4. +6 −10 gpu.vhd
  5. BIN main.bit
  6. +27 −32 main.ucf
  7. +11 −20 main.vhd
  8. +3 −3 main_bd.bmm
  9. +4 −4 points_ram.vhd
  10. +1 −2 proj_matrices.vhd
  11. +13 −10 rt3d.gise
  12. +512 −512 test_triangles.mem
  13. +1 −1 transform_pipeline.vhd
  14. +2 −2 triangle_ram.vhd
View
@@ -8,9 +8,7 @@ entity clock is
port (
papilio_clk : in std_logic;
gpu_clk : out std_logic;
- gpu_clk_n : out std_logic;
- vga_clk : out std_logic;
- vga_clk_n : out std_logic);
+ vga_clk : out std_logic);
end clock;
architecture BEHAVIORAL of clock is
@@ -23,9 +21,7 @@ architecture BEHAVIORAL of clock is
signal CLKFB_IN2 : std_logic;
signal CLK2X_BUF2 : std_logic;
signal CLK_BUF2 : std_logic;
- signal CLK180_BUF2 : std_logic;
signal CLKFX_BUF2 : std_logic;
- signal CLKFX180_BUF2 : std_logic;
begin
@@ -96,21 +92,11 @@ begin
port map (
I=>CLK_BUF2,
O=>vga_clk);
-
- CLK180_BUFG_INST2 : BUFG
- port map (
- I=>CLK180_BUF2,
- O=>vga_clk_n);
-
+
CLKFX_BUFG_INST2 : BUFG
port map (
I=>CLKFX_BUF2,
O=>gpu_clk);
-
- CLKFX180_BUFG_INST2 : BUFG
- port map (
- I=>CLKFX180_BUF2,
- O=>gpu_clk_n);
DCM_SP_INST2 : DCM_SP
@@ -145,11 +131,11 @@ begin
CLK0 => CLK_BUF2,
CLK90 => open,
- CLK180 => CLK180_BUF2,
+ CLK180 => open,
CLK270 => open,
CLKDV => open,
CLKFX => CLKFX_BUF2,
- CLKFX180 => CLKFX180_BUF2,
+ CLKFX180 => open,
CLK2X => CLK2X_BUF2,
CLK2X180 => open);
View
BIN final.bit
Binary file not shown.
View
@@ -21,7 +21,6 @@ port (
t_d : in STD_LOGIC_VECTOR ( 8 downto 0);
clk : in STD_LOGIC;
- clk_n : in STD_LOGIC;
reset : in STD_LOGIC;
line_start : in STD_LOGIC;
y : in STD_LOGIC_VECTOR ( 9 downto 0);
View
16 gpu.vhd
@@ -22,13 +22,11 @@ port (
t_d : in STD_LOGIC_VECTOR ( 8 downto 0);
gpu_clk : in STD_LOGIC;
- gpu_clk_n : in STD_LOGIC;
y : in STD_LOGIC_VECTOR ( 9 downto 0);
line_start : in STD_LOGIC;
reset : in STD_LOGIC;
pixel_clk : in STD_LOGIC;
- pixel_clk_n : in STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 9 downto 0);
color : out STD_LOGIC_VECTOR ( 8 downto 0));
end gpu;
@@ -51,7 +49,6 @@ architecture Behavioral of gpu is
t_d : in STD_LOGIC_VECTOR ( 8 downto 0);
clk : in STD_LOGIC;
- clk_n : in STD_LOGIC;
reset : in STD_LOGIC;
line_start : in STD_LOGIC;
y : in STD_LOGIC_VECTOR ( 9 downto 0);
@@ -127,7 +124,6 @@ begin
t_d => int_t_d,
clk => gpu_clk,
- clk_n => gpu_clk_n,
reset => reset,
line_start => line_start,
y => STD_LOGIC_VECTOR(y),
@@ -138,7 +134,7 @@ begin
triangle_ram_inst: triangle_ram
port map (
- clk => gpu_clk_n,
+ clk => gpu_clk,
i_o => int_t_i,
a_o => int_t_a,
@@ -155,7 +151,7 @@ begin
points_ram_inst: points_ram
port map (
- clk => gpu_clk_n,
+ clk => gpu_clk,
i_o => int_p_i,
x_o => int_p_x,
@@ -172,7 +168,7 @@ begin
ram_even: RAMB16_S9_S9
port map (
- clkA => gpu_clk_n,
+ clkA => not gpu_clk,
enA => y(0),
weA => buffer_we,
ssrA => '0',
@@ -182,7 +178,7 @@ begin
doA => open,
dopA => open,
- clkB => pixel_clk_n,
+ clkB => not pixel_clk,
enB => not y(0),
weB => '0',
ssrB => '0',
@@ -194,7 +190,7 @@ begin
ram_odd: RAMB16_S9_S9
port map (
- clkA => gpu_clk_n,
+ clkA => not gpu_clk,
enA => not y(0),
weA => buffer_we,
ssrA => '0',
@@ -204,7 +200,7 @@ begin
doA => open,
dopA => open,
- clkB => pixel_clk_n,
+ clkB => not pixel_clk,
enB => y(0),
weB => '0',
ssrB => '0',
View
BIN main.bit
Binary file not shown.
View
@@ -38,15 +38,12 @@ NET "vsync" IOSTANDARD = LVTTL;
NET "vsync" LOC = P48;
NET "hsync" IOSTANDARD = LVTTL;
NET "hsync" LOC = P51;
-NET "blue" IOSTANDARD = LVTTL;
-NET "blue" LOC = P56;
+#NET A(2) LOC="P56" | IOSTANDARD=LVTTL ;
#NET A(3) LOC="P58" | IOSTANDARD=LVTTL ;
#NET A(4) LOC="P61" | IOSTANDARD=LVTTL ;
#NET A(5) LOC="P66" | IOSTANDARD=LVTTL ;
-NET "green" IOSTANDARD = LVTTL;
-NET "green" LOC = P67;
-NET "red" IOSTANDARD = LVTTL;
-NET "red" LOC = P75;
+#NET A(6) LOC="P67" | IOSTANDARD=LVTTL ;
+#NET A(7) LOC="P75" | IOSTANDARD=LVTTL ;
#NET A(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
#NET A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
@@ -57,15 +54,14 @@ NET "red" LOC = P75;
#NET A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
#NET A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
-#NET B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
-#NET B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
-#NET B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
-#NET B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
-#NET B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
-#NET B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
-#NET B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
-#NET B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
-
+NET "blue(0)" LOC="P99" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0
+NET "blue(1)" LOC="P97" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1
+NET "blue(2)" LOC="P92" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2
+NET "blue(3)" LOC="P87" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3
+NET "green(0)" LOC="P84" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4
+NET "green(1)" LOC="P82" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5
+NET "green(2)" LOC="P80" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6
+NET "green(3)" LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7
#NET B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
#NET B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
#NET B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
@@ -75,23 +71,22 @@ NET "red" LOC = P75;
#NET B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
#NET B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
-#NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
-#NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
-#NET C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
-#NET C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
-#NET C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
-#NET C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
-#NET C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
-#NET C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
-
-#NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
-#NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
-#NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
-#NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
-#NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
-#NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
-#NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
-#NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
+#NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
+#NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
+NET "vsync" LOC="P116" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C2
+NET "hsync" LOC="P117" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C3
+NET "red(0)" LOC="P118" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C4
+NET "red(1)" LOC="P119" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C5
+NET "red(2)" LOC="P120" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C6
+NET "red(3)" LOC="P121" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C7
+#NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
+#NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
+#NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
+#NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
+#NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
+#NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
+#NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
+#NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
#NET ram_a(0) LOC="P7" | IOSTANDARD=LVTTL; # ADDR0
#NET ram_a(1) LOC="P6" | IOSTANDARD=LVTTL; # ADDR1
View
@@ -10,9 +10,9 @@ port (
papilio_clk : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
- red : out STD_LOGIC;
- green : out STD_LOGIC;
- blue : out STD_LOGIC);
+ red : out STD_LOGIC_VECTOR(3 downto 0);
+ green : out STD_LOGIC_VECTOR(3 downto 0);
+ blue : out STD_LOGIC_VECTOR(3 downto 0));
end main;
architecture Behavioral of main is
@@ -21,9 +21,7 @@ architecture Behavioral of main is
port (
papilio_clk : in std_logic;
gpu_clk : out std_logic;
- gpu_clk_n : out std_logic;
- vga_clk : out std_logic;
- vga_clk_n : out std_logic);
+ vga_clk : out std_logic);
end component;
component gpu is
@@ -44,13 +42,11 @@ architecture Behavioral of main is
t_d : in STD_LOGIC_VECTOR ( 8 downto 0);
gpu_clk : in STD_LOGIC;
- gpu_clk_n : in STD_LOGIC;
reset : in STD_LOGIC;
line_start : in STD_LOGIC;
y : in STD_LOGIC_VECTOR ( 9 downto 0);
pixel_clk : in STD_LOGIC;
- pixel_clk_n : in STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 9 downto 0);
color : out STD_LOGIC_VECTOR ( 8 downto 0));
end component;
@@ -62,15 +58,12 @@ architecture Behavioral of main is
component proj_matrices is
port (
clk : in STD_LOGIC;
- clk_n : in STD_LOGIC;
vbl : in STD_LOGIC;
coefs : out STD_LOGIC_VECTOR ((16*18-1) downto 0));
end component;
signal gpu_clk : std_logic;
- signal gpu_clk_n : std_logic;
signal vga_clk : std_logic;
- signal vga_clk_n : std_logic;
signal matrix : STD_LOGIC_VECTOR((16*18-1) downto 0);
signal reset : STD_LOGIC := '1';
@@ -99,9 +92,7 @@ begin
port map (
papilio_clk => papilio_clk,
gpu_clk => gpu_clk,
- gpu_clk_n => gpu_clk_n,
- vga_clk => vga_clk,
- vga_clk_n => vga_clk_n);
+ vga_clk => vga_clk);
gpu_inst: gpu
port map (
@@ -121,13 +112,11 @@ begin
t_d => t_d,
gpu_clk => gpu_clk,
- gpu_clk_n => gpu_clk_n,
reset => reset,
line_start => line_start,
y => std_logic_vector(y),
pixel_clk => vga_clk,
- pixel_clk_n => vga_clk_n,
x => "0"&std_logic_vector(hcount(9 downto 1)),
color => ram_o);
@@ -137,7 +126,6 @@ begin
proj_matrices_inst : proj_matrices
port map (
clk => vga_clk,
- clk_n => vga_clk_n,
vbl => reset,
coefs => matrix);
@@ -188,9 +176,12 @@ begin
end if;
end process;
- red <= ram_o(2) when hcount<640 and vcount<480 else '0';
- green <= ram_o(1) when hcount<640 and vcount<480 else '0';
- blue <= ram_o(0) when hcount<640 and vcount<480 else '0';
+ red(3 downto 1) <= ram_o(8 downto 6) when hcount<640 and vcount<480 else (others=>'0');
+ green(3 downto 1) <= ram_o(5 downto 3) when hcount<640 and vcount<480 else (others=>'0');
+ blue(3 downto 1) <= ram_o(2 downto 0) when hcount<640 and vcount<480 else (others=>'0');
+ red(0) <= '0';
+ green(0) <= '0';
+ blue(0) <= '0';
end Behavioral;
View
@@ -12,7 +12,7 @@
ADDRESS_SPACE triangles RAMB18 WORD_ADDRESSING [0x00000000:0x000007FF]
BUS_BLOCK
- gpu_inst/triangle_ram_inst/ram [0:8] PLACED = X1Y20;
+ gpu_inst/triangle_ram_inst/ram [0:8] PLACED = X0Y24;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
@@ -25,11 +25,11 @@ END_ADDRESS_SPACE;
ADDRESS_SPACE points RAMB18 WORD_ADDRESSING [0x00000000:0x000007FF]
BUS_BLOCK
- gpu_inst/points_ram_inst/ram0 [0:17] PLACED = X1Y16;
+ gpu_inst/points_ram_inst/ram0 [0:17] PLACED = X0Y6;
END_BUS_BLOCK;
BUS_BLOCK
- gpu_inst/points_ram_inst/ram1 [0:17] PLACED = X1Y14;
+ gpu_inst/points_ram_inst/ram1 [0:17] PLACED = X0Y8;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
View
@@ -52,7 +52,7 @@ begin
INIT_00 => X"0100010001000100ff000100ff0001000100ff000100ff00ff00ff00ff00ff00",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000cc33ff" )
port map (
- clkA => clk,
+ clkA => not clk,
ssrA => '0',
enA => '1',
weA => we,
@@ -62,7 +62,7 @@ begin
doA => open,
dopA => open,
- clkB => clk,
+ clkB => not clk,
ssrB => '0',
enB => '1',
weB => '0',
@@ -77,7 +77,7 @@ begin
INIT_00 => X"000001000000ff00000001000000ff00000001000000ff00000001000000ff00",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000003030303" )
port map (
- clkA => clk,
+ clkA => not clk,
ssrA => '0',
enA => '1',
weA => we,
@@ -87,7 +87,7 @@ begin
doA => open,
dopA => open,
- clkB => clk,
+ clkB => not clk,
ssrB => '0',
enB => '1',
weB => '0',
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