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arduino DS1077 programmable oscillator code
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README
ds1077.pde

README

notes:

tie SDA/SCL to +5v via 3.9Kohm resistors to pull up the I2C bus when not in use.

tie VCC to GND via a 0.1uF and 0.01uF ceramic caps to reduce as much line noise as possible.

the slave address and the r/w bit is automatically sent by the Wire library.
  when you call Wire.beginTransmission(ADDRESS)

"acknowledgment from slave" is taken care of by the wire library.

the "command byte" is the address of the address of the desired register.
  this is sent after Wire.beginTransmission(<address>) with via Wire.send(<COMMAND BYTE>);

if multiple bytes need to be sent, just send them one after another (post acknowledgement)
  finish with Wire.endTransmission();


----------

OUT1 = main oscillator output - freq determined by the control register settings for the prescaler P1
        (mode bits 1M1 & 1M0) and divider N (DIV word)

OUT0 = ref output, OUT0 is taken from the output of the reference select Mux. Its freq is determined
        by the control register settings for CTRL0 and values of Prescaler P0
        (mode bits 0M1 & 0M0)

CTRL0 = multifunctional input pin that can be selected as a MUX SELECT, OUTPUT ENABLE and/or a POWERR-DOWN.
        determined by register values EN0, SEL0, and PDN0 (check table 1)

CTRL1 = mulitfunctinal input pin that can be selected as a OUTPUT ENABLE and/or a POWER-DOWN. determined by
        register PDN1 (table 2)


        
-------------------------------------------------------------------------------
MUX = mode of operation
DIV = operating frequency
BUS = bus settings
-------------------------------------------------------------------------------

MUX WORD:

      MSB                                           LSB   MSB                              LSB
 ______________________________________________________________________________________________
| NAME | * | PDN1 | PDN0 | SEL0 | EN0 | 0M1 | 0M0 | 1M1 || 1M0 | DIV1 | - | - | - | - | - | - |
+---------------------------------------------------------------------------------------------+
|dfault| 0 |   0  |   0  |   1  |  1  |  0  |  0  |  0  ||  0  |   0  | x | x | x | x | x | x |
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 
EN0 (bit)
    1) if (EN0 = 1) and (PDN0 = 0) the CTRL0 pin functions as an Output Enable for OUT0,
       the frequency of the output being determined by the SEL0 bit.
    2) if (PDN0 = 1), the EN0 bit is ignored, CTRL0 will function as a power down, and OUT0 will
       always be enabled on power-up, its freqency being determined by the SEL0 bit.
    3) if (EN0 = 0) the function of CTRL0 is determined by the SEL0 and PDN0 bits

SEL0
    1) if (SEL0 = 1) and (EN0 = PDN0 = 0) the CTRL0 pin determines the state of the MU
       (i.e., the output frequency of OUT0).
    2) If (CTRL0 = 0) the output will be the Master clock frequency
    3) If (CTKL0 = 1) the output will be the frequency of the M prescaler
    4) If either ((EN0 || PDN0) = 1) then SEL0 determines the frequency of OUT0 when enabled.
    5) If (SEL0 = 0) the output will be the Master clock freq.
    6) If (SEL0 = 1) the output will be the freq of the M prescaler

PDN0
    1) If set to 1, causes CTRL0 to perform a power-down function
    2) If set to 0, the function of CTRL0 is determined by EN0 and SEL0

  note: when EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down.

PDN1
    1) if set to 1, CTRL1 will function as a power-down.
    2) if 0, CTRL1 will function as an output enable for OUT1 only.


MUX register functions:
        
DIV WORD:

    MSB                                  LSB   MSB              LSB
    ________________________________________________________________
    | n9 | n8 | n7 | n6 | n5 | n4 | n3 | n2 ||| n1 | n0 |x|x|x|x|x|x|
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
These 10 bits determine the programmable divider (N). The range of divisor
values is from 2-1025, and is equal to the programmed value of N _plus_ 2

e.g., 0 000 000 000 = 0                     (this is the default, btw)
                      n = 0 + 2
                      n = 2
      0 000 000 001 = 1
                      n = 1 + 2
                      n = 3
      1 111 111 111 = 1023
                      n = 1023 + 2
                      n = 1025















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