@@ -4,15 +4,14 @@ author = ["Ben Mezger"]
44date = 2020-05-30T19:58:00-03:00
55slug = " operating-systems"
66tags = [" reading" " books" " cs" " operating-systems"
7- type = " posts "
7+ type = " notes "
88draft = false
99bookCollapseSection = true
1010+++
1111
1212tags
1313: [ Computer Science] ({{< relref "2020-05-31--15-29-21Z--computer_science" >}}) [ Operating Systems] ({{< relref "2020-05-31--15-29-38Z--operating_systems" >}})
1414
15-
1615## READING Operating Systems: Internals and Design Principles (9th Edition) {#reading-operating-systems-internals-and-design-principles--9th-edition}
1716
1817<div class =" table-caption " >
2120</div >
2221
2322| Headline | Time |
24- | ------------------------------------- | ---------- |
23+ | ----------------------------------- | -------- |
2524| ** Total time** | ** 3:24** |
2625| Operating Systems: Internals and... | 3:24 |
2726
28-
2927### Exercises {#exercises}
3028
31291.1. CPU: Takes care of processing data
32- Main memory: Volatile memory for storing data and program instructions
33- Secondary storage: Non-volatile for permantely storing data.
34- I/O: External peripherals such as USB drive, printer and etc.
30+ Main memory: Volatile memory for storing data and program instructions
31+ Secondary storage: Non-volatile for permantely storing data.
32+ I/O: External peripherals such as USB drive, printer and etc.
3533
36341.2. Memory address register (MAR): specifies the memory address for the next
37- read or write.
38- Memory buffer register (MBR): contains data to be written to memory or
39- receives data read from memory.
35+ read or write.
36+ Memory buffer register (MBR): contains data to be written to memory or
37+ receives data read from memory.
4038
41391.3. Processor-memory: Data may be transferred from processor to memory or from
42- memory to processor.
43- Processor-IO: Process may transfer data to I/O module or from I/O module to
44- processor
45- Data processing: Processor may perform arithmetic or logical operation
46- Control: The instruction may specify a different location to fetch the next
47- instruction from, altering the sequence of execution.
40+ memory to processor.
41+ Processor-IO: Process may transfer data to I/O module or from I/O module to
42+ processor
43+ Data processing: Processor may perform arithmetic or logical operation
44+ Control: The instruction may specify a different location to fetch the next
45+ instruction from, altering the sequence of execution.
4846
49471.4. Interrupts the current execution of the CPU. This allows external
50- peripherals to process data while the CPU works on something else. When the
51- data processing is over, the peripheral may trigger an interrupt requesting
52- CPU attention. A CPU interrupt handler may take care of interrupt or ignore it.
48+ peripherals to process data while the CPU works on something else. When the
49+ data processing is over, the peripheral may trigger an interrupt requesting
50+ CPU attention. A CPU interrupt handler may take care of interrupt or ignore it.
5351
54521.5. There are two types of handling interrupts: sequentially or by
55- priority-policy. In sequential interrupts, if an interrupt happens within the
56- handler of a current interrupt, the interrupt will be ignored for the moment
57- by setting a pending interrupt. After it the current interrupt has been
58- dealt, it then treats the next pending interrupt. Priority-based interrupts
59- allows one interrupt to be handled by priority. Whiling handling one
60- interrupt, if another interrupt occurs and the priority is higher than the
61- current interrupt being dealt, it stores the current context and handles the
62- higher priority interrupt.
53+ priority-policy. In sequential interrupts, if an interrupt happens within the
54+ handler of a current interrupt, the interrupt will be ignored for the moment
55+ by setting a pending interrupt. After it the current interrupt has been
56+ dealt, it then treats the next pending interrupt. Priority-based interrupts
57+ allows one interrupt to be handled by priority. Whiling handling one
58+ interrupt, if another interrupt occurs and the priority is higher than the
59+ current interrupt being dealt, it stores the current context and handles the
60+ higher priority interrupt.
6361
64621.6. Cost, speed, size are characteristics that are important
6563
6664<!-- list-separator-->
6765
68- - Notes
66+ - Notes
6967
70- <!-- list-separator-->
68+ <!-- list-separator-->
7169
72- - Program execution
70+ - Program execution
7371
74- A program consists of a set of instructions stored in memory. The processor
75- fetches one instruction at a time and executes each instruction. The processing
76- required for one instruction is called the ** instruction cycle** . The instruction
77- cycle is composed of three main stages:
72+ A program consists of a set of instructions stored in memory. The processor
73+ fetches one instruction at a time and executes each instruction. The processing
74+ required for one instruction is called the ** instruction cycle** . The instruction
75+ cycle is composed of three main stages:
7876
79- 1 . Fetch stage: The process fetches an instruction from memory. Most processor
80- hold some type of PC (Program counter) register which points to the next
81- instruction in memory. Each time a new instruction has been fetched, the PC
82- is incremented to the next instruction. The fetch stage usually consists of the
83- following "substages"
84- - Address of PC is copied to the MAR (Memory address register), which either
85- stores the memory address from where data will be fetched or the address to
86- which data will be sent or stored.
77+ 1 . Fetch stage: The process fetches an instruction from memory. Most processor
78+ hold some type of PC (Program counter) register which points to the next
79+ instruction in memory. Each time a new instruction has been fetched, the PC
80+ is incremented to the next instruction. The fetch stage usually consists of the
81+ following "substages"
82+ - Address of PC is copied to the MAR (Memory address register), which either
83+ stores the memory address from where data will be fetched or the address to
84+ which data will be sent or stored.
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