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  1. pyvivado Public

    Python tools for Vivado Projects

    Python 64 12

  2. slvcodec Public

    Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.

    Python 8 3

  3. axilent Public

    Python to AXI4

    Python 7 2

  4. Add generators to fusesoc so that depenedencies can be generated from generic parameters.

    Python 2 2

  5. rust_hdl Public

    Forked from VHDL-LS/rust_hdl


67 contributions in the last year

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Contribution activity

October 2021

benreynwar has no activity yet for this period.

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