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Implementation of BESM-6 clone in Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 333 Commits
board		board
model		model
rtl		rtl
test		test
toolchain		toolchain
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md

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MESM-6

Implementation of BESM-6 compatible processor in Verilog.

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Implementation of BESM-6 clone in Verilog

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