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BaseJump STL: A Standard Template Library for SystemVerilog
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bsg_async bsg_async_credit_counter add async reset procedure Mar 8, 2019
bsg_cache only consider tagst_op if v_i = 1 (#23) Apr 19, 2019
bsg_chip add stats Feb 15, 2016
bsg_clk_gen instantiate delay lines in bsg_dram_clk_gen Sep 20, 2018
bsg_comm_link fixes for bsg_misc_set1 Jun 21, 2018
bsg_dataflow Converging on a better interface. Mar 20, 2019
bsg_dram_ctrl
bsg_fpu updated README Jun 26, 2018
bsg_fsb
bsg_legacy
bsg_math/bsg_hypotenuse fixes for bsg_misc_set1 Jun 21, 2018
bsg_mem Adding verilator version number Apr 6, 2019
bsg_mesosync_io fixes for bsg_misc_set1 Jun 21, 2018
bsg_misc improve verilator compatibility Apr 13, 2019
bsg_noc Minor linter fixes Apr 1, 2019
bsg_riscv added bsg_vscale_pkg containing vscale params Mar 21, 2016
bsg_tag move to legacy Apr 6, 2019
bsg_test [trace-replay] added the general trace-replay module with examples. Jan 6, 2019
common removed redundant range code from mbt_fifo_vl Nov 6, 2014
hard Updates to pickle_40 harden memories. Apr 1, 2019
testing add several test cases Apr 13, 2019
.gitignore bsg_cache_dma_pkt Aug 29, 2018
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LICENSE minor change Aug 24, 2016
README.md Update README.md Apr 6, 2019
README_contributing

README.md

BaseJump Standard Template Library (STL) Repository

This library is a comprehensive hardware library for SystemVerilog that seeks to contain all of the commonly used HW primitives.

See this paper http://cseweb.ucsd.edu/~mbtaylor/papers/Taylor_DAC_BaseJump_STL_2018.pdf which describes the design and usage.

Contents

  • bsg_async

This is for asynchronous building blocks, like the bsg_async_fifo, synchronizers, and credit counters.

  • bsg_misc

Small, miscellaneous building blocks, like counters, reset timers, gray to binary coders, etc.

  • bsg_fsb

Bsg front side bus modules; also murn interfacing code.

  • bsg_comm_link

Source synchronous communication interface. (Also used as FPGA bridge).

  • bsg_dataflow

For standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines, sbox units, compare_and_swap, and array pack/unpack.

  • bsg_test

Data, clock, and reset generator for test benches.

  • testing

Mirrors the other directories, with tests.

  • hard

Mirrors other directories, contains replacement files for specific process technologies.

Contact

Email: taylor-bsg@googlegroups.com

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