BaseJump Standard Template Library (STL) Repository
This library is a comprehensive hardware library for SystemVerilog that seeks to contain all of the commonly used HW primitives.
See this paper docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf which describes the design and usage.
Please also see the BSG SystemVerilog Style Guide which describes many of the conventions used in this library, including the variants of the valid/ready handshaking protocols.
Small, miscellaneous building blocks, like counters, reset timers, gray to binary coders, etc.
This is for asynchronous building blocks, like the bsg_async_fifo, synchronizers, and credit counters.
Bsg front side bus modules; also murn interfacing code.
Unidirectional off-chip high-speed source synchronous communication interface. (also used as FPGA bridge).
For standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines, sbox units, compare_and_swap, and array pack/unpack.
Data, clock, and reset generator for test benches.
Mirrors the other directories, with tests.
Mirrors other directories, contains replacement files for specific process technologies.