Skip to content
BaseJump STL: A Standard Template Library for SystemVerilog
Branch: master
Clone or download
tommydcjung Merge pull request #52 from bespoke-silicon-group/wormhole_bsg_noc_link
Changing wormhole router to use bsg_noc_links instead of ready-valid
Latest commit e4c561a May 23, 2019
Type Name Latest commit message Commit time
Failed to load latest commit information.
bsg_async bsg_async_credit_counter add async reset procedure Mar 8, 2019
bsg_cache Update bsg_cache.v May 17, 2019
bsg_chip add stats Feb 15, 2016
bsg_clk_gen instantiate delay lines in bsg_dram_clk_gen Sep 20, 2018
bsg_comm_link fixes for bsg_misc_set1 Jun 21, 2018
bsg_dataflow Converging on a better interface. Mar 20, 2019
bsg_dmc fixed a bug of dqs filter May 20, 2019
bsg_fpu update README May 7, 2019
bsg_fsb Merge branch 'master' of Dec 7, 2018
bsg_legacy improvements to fsb, remove warning on bsg_mem_1rw_sync Jul 21, 2015
bsg_math/bsg_hypotenuse fixes for bsg_misc_set1 Jun 21, 2018
bsg_mem Adding verilator version number Apr 6, 2019
bsg_mesosync_io fixes for bsg_misc_set1 Jun 21, 2018
bsg_misc fix N=1 case for bsg_priority_encode_one_hot_out.v; update bsg_mem_ba… May 16, 2019
bsg_noc Changing wormhole adapters to use bsg_noc_link instead of ready-valid May 22, 2019
bsg_riscv added bsg_vscale_pkg containing vscale params Mar 21, 2016
bsg_tag move to legacy Apr 6, 2019
bsg_test [trace-replay] added the general trace-replay module with examples. Jan 6, 2019
common removed redundant range code from mbt_fifo_vl Nov 6, 2014
hard Merge pull request #31 from bespoke-silicon-group/hard_tsmc_180_250 May 15, 2019
testing Merge pull request #52 from bespoke-silicon-group/wormhole_bsg_noc_link May 23, 2019
.gitignore bsg_cache_dma_pkt Aug 29, 2018
.gitmodules Vscale code added to the repo Mar 2, 2016
LICENSE minor change Aug 24, 2016 Update Apr 6, 2019
README_contributing README_contributing edited online with Bitbucket Feb 13, 2018

BaseJump Standard Template Library (STL) Repository

This library is a comprehensive hardware library for SystemVerilog that seeks to contain all of the commonly used HW primitives.

See this paper which describes the design and usage.


  • bsg_async

This is for asynchronous building blocks, like the bsg_async_fifo, synchronizers, and credit counters.

  • bsg_misc

Small, miscellaneous building blocks, like counters, reset timers, gray to binary coders, etc.

  • bsg_fsb

Bsg front side bus modules; also murn interfacing code.

  • bsg_comm_link

Source synchronous communication interface. (Also used as FPGA bridge).

  • bsg_dataflow

For standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines, sbox units, compare_and_swap, and array pack/unpack.

  • bsg_test

Data, clock, and reset generator for test benches.

  • testing

Mirrors the other directories, with tests.

  • hard

Mirrors other directories, contains replacement files for specific process technologies.



You can’t perform that action at this time.