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Tile based architecture designed for computing efficiency, scalability and generality
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bornaehsani Merge pull request #27 from bespoke-silicon-group/bsg_id_calculation_…
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Bug fix bsg_id calculation from __bsg_x/y
Latest commit c179c82 May 11, 2019

README.md

Overview

This repo contains the bsg_manycore source code designed by Bespoke Silicon Group@University of Washington.

The tile based architecture is designed for computing efficiency, scalability and generality. The two main components are:

  • Computing Node: In-house RISC-V 32IM compatible core runs at 1.4GHz@16nm, but nodes also can be any other accelerators.
  • Mesh Network : Dimension ordered, single flit network with inter-nodes synchronization primitives (mutex, barrier etc.)

Without any customized circuit, a 16nm prototype chip that holds 16x31 tiles on a 4.5x3.4 mm^2 die space achieves 812,350 aggregated CoreMark score.

Documentation

  1. Chip gallery, publications, and artworks:
  2. Bleeding edge features and proceedings:

Tutorial

Comming Soon!

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