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Overview

This repo contains the bsg_manycore source code with contributions from the Bespoke Silicon Group and others.

The tile based architecture is designed for computing efficiency, scalability and generality. The two main components are:

  • Computing Node: Purpose-designed RISC-V 32IMF compatible core runs at 1.4GHz@16nm, but nodes also can be any other accelerators.
  • Mesh or Ruche Network : Dimension ordered, single flit network with inter-nodes synchronization primitives (mutex, barrier etc.)

Without any custom circuits, a 16nm prototype chip with 16x31 tiles on a 4.5x3.4 mm^2 die space achieves 812,350 aggregated CoreMark score, a world record. Many improvements have been made since this previous version.

Documentation

  1. Chip gallery, publications, and artworks:
  2. Bleeding edge features and proceedings:

Initial Setup for running programs

Above this directory:

  • Checkout basejump_stl; cd into imports directory and type make DRAMSim3
  • Checkout bsg_cadenv if you are a BSG group member

In this directory:

  • make checkout_submodules: To update all submodules in imports/.
  • make tools: To install software toolchain required running programs on BSG Manycore. (This build uses 12-16 threads by default.)
  • make machines: Compile simulation executables in machines/. If you do not have bsg_cadenv, then you will have to set some VCS-related variables.
  • Edit BSG_MACHINE_PATH in software/mk/Makefile.paths to choose the machine to run somd programs on.
  • go into software/spmd/bsg_barrier and type make to run a test!

Contributions

If you're developing on a branch called mybranch, please pull a branch called ci_mybranch based on mybranch to run CI and mybranch. It's advised to keep working on mybranch for incremental updates and rebase ci_mybranch on mybranch when it's ready for another CI run.

Tutorial

Comming Soon!

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Tile based architecture designed for computing efficiency, scalability and generality

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