forked from sutajiokousagi/betrusted-soc
-
-
Notifications
You must be signed in to change notification settings - Fork 23
/
Copy pathbetrusted-soc.py
executable file
·1821 lines (1613 loc) · 90.7 KB
/
betrusted-soc.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "vivado"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
import litex.soc.doc as lxsocdoc
from pathlib import Path
import subprocess
import sys
from random import SystemRandom
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.cdc import MultiReg
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.cores.clock import S7MMCM, S7IDELAYCTRL
from litex.soc.cores.i2s import S7I2S
from litex.soc.cores.spi_opi import S7SPIOPI
from litex.soc.integration.soc import SoCRegion
from gateware import info
from gateware import sram_32
from gateware import memlcd
from gateware import spi_7series as spi
from gateware import messible
from gateware import i2c
from gateware import ticktimer
from gateware import spinor
from gateware import keyboard
from gateware.trng.ring_osc_v2 import TrngRingOscV2
from gateware import aes_opentitan as aes
from gateware import sha2_opentitan as sha2
from gateware import sha512_opentitan as sha512
from gateware.curve25519.engine import Engine
from gateware import jtag_phy
from valentyusb.usbcore.cpu.eptri import TriEndpointInterface
from valentyusb.usbcore.io import IoBuf
# IOs ----------------------------------------------------------------------------------------------
_io_pvt = [ # PVT-generation I/Os
("clk12", 0, Pins("R3"), IOStandard("LVCMOS18")),
("analog", 0,
Subsignal("usbdet_p", Pins("C3"), IOStandard("LVCMOS33")), # DVT
Subsignal("usbdet_n", Pins("A3"), IOStandard("LVCMOS33")), # DVT
Subsignal("vbus_div", Pins("C4"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise0", Pins("C5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise1", Pins("A8"), IOStandard("LVCMOS33")), # DVT
# diff grounds
Subsignal("usbdet_p_n", Pins("B3"), IOStandard("LVCMOS33")), # DVT
Subsignal("usbdet_n_n", Pins("A2"), IOStandard("LVCMOS33")), # DVT
Subsignal("vbus_div_n", Pins("B4"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise0_n", Pins("B5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise1_n", Pins("A7"), IOStandard("LVCMOS33")), # DVT
# dedicated pins (no I/O standard applicable)
Subsignal("ana_vn", Pins("K9")),
Subsignal("ana_vp", Pins("J10")),
),
("jtag", 0,
Subsignal("tck", Pins("U11"), IOStandard("LVCMOS18")), # DVT
Subsignal("tms", Pins("P6"), IOStandard("LVCMOS18")), # DVT
Subsignal("tdi", Pins("P7"), IOStandard("LVCMOS18")), # DVT
Subsignal("tdo", Pins("R6"), IOStandard("LVCMOS18")), # DVT
),
("usb", 0,
Subsignal("d_p", Pins("C1"), IOStandard("LVCMOS33"), Misc("DRIVE=12")), # DVT
Subsignal("d_n", Pins("B1"), IOStandard("LVCMOS33"), Misc("DRIVE=12")), # DVT
Subsignal("pullup_p", Pins("D1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")), # DVT
Misc("SLEW=SLOW"),
),
("lpclk", 0, Pins("N15"), IOStandard("LVCMOS18")), # wifi_lpclk
# Power control signals
("power", 0,
Subsignal("audio_on", Pins("B7"), IOStandard("LVCMOS33")), # DVT
Subsignal("fpga_sys_on", Pins("A5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noisebias_on", Pins("E17"), IOStandard("LVCMOS33")), # DVT
Subsignal("allow_up5k_n", Pins("B14"), IOStandard("LVCMOS33")),
Subsignal("pwr_s0", Pins("U6"), IOStandard("LVCMOS18")),
Subsignal("pwr_s1", Pins("L13"), IOStandard("LVCMOS18")), # DVT
# Noise generator
Subsignal("noise_on", Pins("P14 R13"), IOStandard("LVCMOS18")),
# vibe motor
Subsignal("vibe_on", Pins("G13"), IOStandard("LVCMOS33")), # PVT
# reset EC
Subsignal("reset_ec", Pins("M6"), IOStandard("LVCMOS18")), # PVT -- allow FPGA to recover crashed EC (invert polarity)
# USB_CC DFP attach
Subsignal("cc_id", Pins("D18"), IOStandard("LVCMOS33")), # DVT
# turn on the UP5K in case we are woken up by RTC
Subsignal("up5k_on", Pins("G18"), IOStandard("LVCMOS33")), # DVT -- T_TO_U_ON
Subsignal("boostmode", Pins("H16"), IOStandard("LVCMOS33")), # PVT - for sourcing power in USB host mode
Subsignal("selfdestruct", Pins("J14"), IOStandard("LVCMOS33")), # PVT - cut power to BBRAM key and unit in an annoying-to-reset fashion
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# Audio interface
("i2s", 0,
Subsignal("clk", Pins("D12")),
Subsignal("tx", Pins("E13")), # au_sdi1
Subsignal("rx", Pins("C13")), # au_sdo1
Subsignal("sync", Pins("D14")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
("au_mclk", 0, Pins("E12"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW"), Misc("DRIVE=8")),
# I2C1 bus -- to RTC and audio CODEC
("i2c", 0,
Subsignal("scl", Pins("G2"), IOStandard("LVCMOS33")), # DVT
Subsignal("sda", Pins("F2"), IOStandard("LVCMOS33")), # DVT
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
# RTC interrupt
("rtc_irq", 0, Pins("N5"), IOStandard("LVCMOS18")),
# COM interface to UP5K
("com", 0,
Subsignal("csn", Pins("T15"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
Subsignal("cipo", Pins("P16"), IOStandard("LVCMOS18")),
Subsignal("copi", Pins("N18"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
Subsignal("sclk", Pins("R16"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
),
("com_irq", 0, Pins("M16"), IOStandard("LVCMOS18")),
# Top-side internal FPC header
# Add USB PU/PD config to the GPIO cluster, see comment
("gpio", 0, Pins("F14 F15 E16 G15 H15 G16 F18 E18"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), # PVT
#("usb_alt", 0,
# Subsignal("pulldn_p", Pins("C2"), IOStandard("LVCMOS33")), # DVT
# Subsignal("pullup_n", Pins("B2"), IOStandard("LVCMOS33")), # DVT
# Subsignal("pulldn_n", Pins("A4"), IOStandard("LVCMOS33")), # DVT
# Misc("DRIVE=4"), Misc("SLEW=SLOW"),
# ),
# Keyboard scan matrix
("kbd", 0,
# "key" 0-8 are rows, 9-18 are columns
# column scan with 1's, so PD to default 0
Subsignal("row", Pins("A15 A17 A16 A14 C17 B16 B17 C14 B15"), Misc("PULLDOWN True")), # DVT
Subsignal("col", Pins("B13 C18 E14 D15 B18 D16 D17 F13 E15 A13")), # DVT
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# LCD interface
("lcd", 0,
Subsignal("sclk", Pins("H17")), # DVT
Subsignal("scs", Pins("G17")), # DVT
Subsignal("si", Pins("H18")), # DVT
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# SPI Flash
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("copi", Pins("K17")),
Subsignal("cipo", Pins("K18")),
Subsignal("wp", Pins("L14")), # provisional
Subsignal("hold", Pins("M15")), # provisional
IOStandard("LVCMOS18")
),
("spiflash_8x", 0, # clock needs a separate override to meet timing
Subsignal("cs_n", Pins("M13")),
Subsignal("dq", Pins("K17 K18 L14 M15 L17 L18 M14 N14")),
Subsignal("dqs", Pins("R14")),
Subsignal("ecs_n", Pins("L16")),
Subsignal("sclk", Pins("C12")), # DVT
IOStandard("LVCMOS18"),
Misc("SLEW=SLOW"),
),
# SRAM
("sram", 0,
Subsignal("adr", Pins(
"V12 M5 P5 N4 V14 M3 R17 U15",
"M4 L6 K3 R18 U16 K1 R5 T2",
"U1 N1 L5 K2 M18 T6"),
IOStandard("LVCMOS18")),
Subsignal("ce_n", Pins("V5"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("oe_n", Pins("U12"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("we_n", Pins("K4"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("zz_n", Pins("V17"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("d", Pins(
"M2 R4 P2 L4 L1 M1 R1 P1",
"U3 V2 V4 U2 N2 T1 K6 J6",
"V16 V15 U17 U18 P17 T18 P18 M17",
"N3 T4 V13 P15 T14 R15 T3 R7"),
IOStandard("LVCMOS18")),
Subsignal("dm_n", Pins("V3 R2 T5 T13"), IOStandard("LVCMOS18")),
),
]
_io_dvt_modnoise = [ # DVT-generation I/Os for noise modulator test
("clk12", 0, Pins("R3"), IOStandard("LVCMOS18")),
("analog", 0,
Subsignal("usbdet_p", Pins("C3"), IOStandard("LVCMOS33")), # DVT
Subsignal("usbdet_n", Pins("A3"), IOStandard("LVCMOS33")), # DVT
Subsignal("vbus_div", Pins("C4"), IOStandard("LVCMOS33")), # DVT
#Subsignal("noise0", Pins("C5"), IOStandard("LVCMOS33")), # DVT rerouted for test
#Subsignal("noise1", Pins("A8"), IOStandard("LVCMOS33")), # DVT rerouted for test
# diff grounds
Subsignal("usbdet_p_n", Pins("B3"), IOStandard("LVCMOS33")), # DVT
Subsignal("usbdet_n_n", Pins("A2"), IOStandard("LVCMOS33")), # DVT
Subsignal("vbus_div_n", Pins("B4"), IOStandard("LVCMOS33")), # DVT
#Subsignal("noise0_n", Pins("B5"), IOStandard("LVCMOS33")), # DVT
#Subsignal("noise1_n", Pins("A7"), IOStandard("LVCMOS33")), # DVT
# dedicated pins (no I/O standard applicable)
Subsignal("ana_vn", Pins("K9")),
Subsignal("ana_vp", Pins("J10")),
),
("jtag", 0,
Subsignal("tck", Pins("U11"), IOStandard("LVCMOS18")), # DVT
Subsignal("tms", Pins("P6"), IOStandard("LVCMOS18")), # DVT
Subsignal("tdi", Pins("P7"), IOStandard("LVCMOS18")), # DVT
Subsignal("tdo", Pins("R6"), IOStandard("LVCMOS18")), # DVT
),
("usb", 0,
Subsignal("d_p", Pins("C1"), IOStandard("LVCMOS33"), Misc("DRIVE=12")), # DVT
Subsignal("d_n", Pins("B1"), IOStandard("LVCMOS33"), Misc("DRIVE=12")), # DVT
Subsignal("pullup_p", Pins("D1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")), # DVT
Misc("SLEW=SLOW"),
),
("lpclk", 0, Pins("N15"), IOStandard("LVCMOS18")), # wifi_lpclk
# Power control signals
("power", 0,
Subsignal("audio_on", Pins("B7"), IOStandard("LVCMOS33")), # DVT
Subsignal("fpga_sys_on", Pins("A5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noisebias_on", Pins("E17"), IOStandard("LVCMOS33")), # DVT
Subsignal("allow_up5k_n", Pins("B14"), IOStandard("LVCMOS33")),
Subsignal("pwr_s0", Pins("U6"), IOStandard("LVCMOS18")),
Subsignal("pwr_s1", Pins("L13"), IOStandard("LVCMOS18")), # DVT
# Noise generator
# Subsignal("noise_on", Pins("P14 R13"), IOStandard("LVCMOS18")), ## rerouted for test
# vibe motor
Subsignal("vibe_on", Pins("H15"), IOStandard("LVCMOS33")), # DVT
# reset EC
Subsignal("reset_ec_n", Pins("M6"), IOStandard("LVCMOS18")), # DVT -- allow FPGA to recover crashed EC
# USB_CC DFP attach
Subsignal("cc_id", Pins("D18"), IOStandard("LVCMOS33")), # DVT
# turn on the UP5K in case we are woken up by RTC
Subsignal("up5k_on", Pins("E18"), IOStandard("LVCMOS33")), # DVT -- T_TO_U_ON
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# Audio interface
("i2s", 0,
Subsignal("clk", Pins("D12")),
Subsignal("tx", Pins("E13")), # au_sdi1
Subsignal("rx", Pins("C13")), # au_sdo1
Subsignal("sync", Pins("D14")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
("au_mclk", 0, Pins("E12"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW"), Misc("DRIVE=8")),
# I2C1 bus -- to RTC and audio CODEC
("i2c", 0,
Subsignal("scl", Pins("G2"), IOStandard("LVCMOS33")), # DVT
Subsignal("sda", Pins("F2"), IOStandard("LVCMOS33")), # DVT
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
# RTC interrupt
("rtc_irq", 0, Pins("N5"), IOStandard("LVCMOS18")),
# COM interface to UP5K
("com", 0,
Subsignal("csn", Pins("T15"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
Subsignal("cipo", Pins("P16"), IOStandard("LVCMOS18")),
Subsignal("copi", Pins("N18"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
Subsignal("sclk", Pins("R16"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
),
("com_irq", 0, Pins("M16"), IOStandard("LVCMOS18")),
# Top-side internal FPC header
# Add USB PU/PD config to the GPIO cluster, see comment
("gpio", 0, Pins("F14 F15 E16 G15 G16 G13"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), # DVT
# Noise generator
("modnoise", 0,
Subsignal("noise_on", Pins("R13"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=12")),
Subsignal("noise_in", Pins("P14"), IOStandard("LVCMOS18")),
Subsignal("phase0", Pins("C5"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
Subsignal("phase1", Pins("A8"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
),
# ("usb_alt", 0,
# Subsignal("pulldn_p", Pins("C2"), IOStandard("LVCMOS33")), # DVT
# Subsignal("pullup_n", Pins("B2"), IOStandard("LVCMOS33")), # DVT
# Subsignal("pulldn_n", Pins("A4"), IOStandard("LVCMOS33")), # DVT
# Misc("DRIVE=4"), Misc("SLEW=SLOW"),
# ),
# Keyboard scan matrix
("kbd", 0,
# "key" 0-8 are rows, 9-18 are columns
# column scan with 1's, so PD to default 0
Subsignal("row", Pins("A15 A17 A16 A14 C17 B16 B17 C14 B15"), Misc("PULLDOWN True")), # DVT
Subsignal("col", Pins("B13 C18 E14 D15 B18 D16 D17 F13 E15 A13")), # DVT
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# LCD interface
("lcd", 0,
Subsignal("sclk", Pins("H17")), # DVT
Subsignal("scs", Pins("G17")), # DVT
Subsignal("si", Pins("H18")), # DVT
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# SPI Flash
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("copi", Pins("K17")),
Subsignal("cipo", Pins("K18")),
Subsignal("wp", Pins("L14")), # provisional
Subsignal("hold", Pins("M15")), # provisional
IOStandard("LVCMOS18")
),
("spiflash_8x", 0, # clock needs a separate override to meet timing
Subsignal("cs_n", Pins("M13")),
Subsignal("dq", Pins("K17 K18 L14 M15 L17 L18 M14 N14")),
Subsignal("dqs", Pins("R14")),
Subsignal("ecs_n", Pins("L16")),
Subsignal("sclk", Pins("C12")), # DVT
IOStandard("LVCMOS18"),
Misc("SLEW=SLOW"),
),
# SRAM
("sram", 0,
Subsignal("adr", Pins(
"V12 M5 P5 N4 V14 M3 R17 U15",
"M4 L6 K3 R18 U16 K1 R5 T2",
"U1 N1 L5 K2 M18 T6"),
IOStandard("LVCMOS18")),
Subsignal("ce_n", Pins("V5"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("oe_n", Pins("U12"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("we_n", Pins("K4"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("zz_n", Pins("V17"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("d", Pins(
"M2 R4 P2 L4 L1 M1 R1 P1",
"U3 V2 V4 U2 N2 T1 K6 J6",
"V16 V15 U17 U18 P17 T18 P18 M17",
"N3 T4 V13 P15 T14 R15 T3 R7"),
IOStandard("LVCMOS18")),
Subsignal("dm_n", Pins("V3 R2 T5 T13"), IOStandard("LVCMOS18")),
),
]
_io_dvt = [ # DVT-generation I/Os
("clk12", 0, Pins("R3"), IOStandard("LVCMOS18")),
("analog", 0,
Subsignal("usbdet_p", Pins("C3"), IOStandard("LVCMOS33")), # DVT
Subsignal("usbdet_n", Pins("A3"), IOStandard("LVCMOS33")), # DVT
Subsignal("vbus_div", Pins("C4"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise0", Pins("C5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise1", Pins("A8"), IOStandard("LVCMOS33")), # DVT
# diff grounds
Subsignal("usbdet_p_n", Pins("B3"), IOStandard("LVCMOS33")), # DVT
Subsignal("usbdet_n_n", Pins("A2"), IOStandard("LVCMOS33")), # DVT
Subsignal("vbus_div_n", Pins("B4"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise0_n", Pins("B5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noise1_n", Pins("A7"), IOStandard("LVCMOS33")), # DVT
# dedicated pins (no I/O standard applicable)
Subsignal("ana_vn", Pins("K9")),
Subsignal("ana_vp", Pins("J10")),
),
("jtag", 0,
Subsignal("tck", Pins("U11"), IOStandard("LVCMOS18")), # DVT
Subsignal("tms", Pins("P6"), IOStandard("LVCMOS18")), # DVT
Subsignal("tdi", Pins("P7"), IOStandard("LVCMOS18")), # DVT
Subsignal("tdo", Pins("R6"), IOStandard("LVCMOS18")), # DVT
),
("usb", 0,
Subsignal("d_p", Pins("C1"), IOStandard("LVCMOS33"), Misc("DRIVE=12")), # DVT
Subsignal("d_n", Pins("B1"), IOStandard("LVCMOS33"), Misc("DRIVE=12")), # DVT
Subsignal("pullup_p", Pins("D1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")), # DVT
Misc("SLEW=SLOW"),
),
("lpclk", 0, Pins("N15"), IOStandard("LVCMOS18")), # wifi_lpclk
# Power control signals
("power", 0,
Subsignal("audio_on", Pins("B7"), IOStandard("LVCMOS33")), # DVT
Subsignal("fpga_sys_on", Pins("A5"), IOStandard("LVCMOS33")), # DVT
Subsignal("noisebias_on", Pins("E17"), IOStandard("LVCMOS33")), # DVT
Subsignal("allow_up5k_n", Pins("B14"), IOStandard("LVCMOS33")),
Subsignal("pwr_s0", Pins("U6"), IOStandard("LVCMOS18")),
Subsignal("pwr_s1", Pins("L13"), IOStandard("LVCMOS18")), # DVT
# Noise generator
Subsignal("noise_on", Pins("P14 R13"), IOStandard("LVCMOS18")),
# vibe motor
Subsignal("vibe_on", Pins("H15"), IOStandard("LVCMOS33")), # DVT
# reset EC
Subsignal("reset_ec_n", Pins("M6"), IOStandard("LVCMOS18")), # DVT -- allow FPGA to recover crashed EC
# USB_CC DFP attach
Subsignal("cc_id", Pins("D18"), IOStandard("LVCMOS33")), # DVT
# turn on the UP5K in case we are woken up by RTC
Subsignal("up5k_on", Pins("E18"), IOStandard("LVCMOS33")), # DVT -- T_TO_U_ON
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# Audio interface
("i2s", 0,
Subsignal("clk", Pins("D12")),
Subsignal("tx", Pins("E13")), # au_sdi1
Subsignal("rx", Pins("C13")), # au_sdo1
Subsignal("sync", Pins("D14")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
("au_mclk", 0, Pins("E12"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW"), Misc("DRIVE=8")),
# I2C1 bus -- to RTC and audio CODEC
("i2c", 0,
Subsignal("scl", Pins("G2"), IOStandard("LVCMOS33")), # DVT
Subsignal("sda", Pins("F2"), IOStandard("LVCMOS33")), # DVT
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
# RTC interrupt
("rtc_irq", 0, Pins("N5"), IOStandard("LVCMOS18")),
# COM interface to UP5K
("com", 0,
Subsignal("csn", Pins("T15"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
Subsignal("cipo", Pins("P16"), IOStandard("LVCMOS18")),
Subsignal("copi", Pins("N18"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
Subsignal("sclk", Pins("R16"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW"), Misc("DRIVE=4")),
),
("com_irq", 0, Pins("M16"), IOStandard("LVCMOS18")),
# Top-side internal FPC header
# Add USB PU/PD config to the GPIO cluster, see comment
("gpio", 0, Pins("F14 F15 E16 G15 G16 G13"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), # DVT
#("usb_alt", 0,
# Subsignal("pulldn_p", Pins("C2"), IOStandard("LVCMOS33")), # DVT
# Subsignal("pullup_n", Pins("B2"), IOStandard("LVCMOS33")), # DVT
# Subsignal("pulldn_n", Pins("A4"), IOStandard("LVCMOS33")), # DVT
# Misc("DRIVE=4"), Misc("SLEW=SLOW"),
# ),
# Keyboard scan matrix
("kbd", 0,
# "key" 0-8 are rows, 9-18 are columns
# column scan with 1's, so PD to default 0
Subsignal("row", Pins("A15 A17 A16 A14 C17 B16 B17 C14 B15"), Misc("PULLDOWN True")), # DVT
Subsignal("col", Pins("B13 C18 E14 D15 B18 D16 D17 F13 E15 A13")), # DVT
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# LCD interface
("lcd", 0,
Subsignal("sclk", Pins("H17")), # DVT
Subsignal("scs", Pins("G17")), # DVT
Subsignal("si", Pins("H18")), # DVT
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# SPI Flash
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("copi", Pins("K17")),
Subsignal("cipo", Pins("K18")),
Subsignal("wp", Pins("L14")), # provisional
Subsignal("hold", Pins("M15")), # provisional
IOStandard("LVCMOS18")
),
("spiflash_8x", 0, # clock needs a separate override to meet timing
Subsignal("cs_n", Pins("M13")),
Subsignal("dq", Pins("K17 K18 L14 M15 L17 L18 M14 N14")),
Subsignal("dqs", Pins("R14")),
Subsignal("ecs_n", Pins("L16")),
Subsignal("sclk", Pins("C12")), # DVT
IOStandard("LVCMOS18"),
Misc("SLEW=SLOW"),
),
# SRAM
("sram", 0,
Subsignal("adr", Pins(
"V12 M5 P5 N4 V14 M3 R17 U15",
"M4 L6 K3 R18 U16 K1 R5 T2",
"U1 N1 L5 K2 M18 T6"),
IOStandard("LVCMOS18")),
Subsignal("ce_n", Pins("V5"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("oe_n", Pins("U12"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("we_n", Pins("K4"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("zz_n", Pins("V17"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("d", Pins(
"M2 R4 P2 L4 L1 M1 R1 P1",
"U3 V2 V4 U2 N2 T1 K6 J6",
"V16 V15 U17 U18 P17 T18 P18 M17",
"N3 T4 V13 P15 T14 R15 T3 R7"),
IOStandard("LVCMOS18")),
Subsignal("dm_n", Pins("V3 R2 T5 T13"), IOStandard("LVCMOS18")),
),
]
_io_evt = [
("clk12", 0, Pins("R3"), IOStandard("LVCMOS18")),
("analog", 0,
Subsignal("usbc_cc1", Pins("C17"), IOStandard("LVCMOS33")),
Subsignal("usbc_cc2", Pins("E16"), IOStandard("LVCMOS33")),
Subsignal("vbus_div", Pins("E12"), IOStandard("LVCMOS33")),
Subsignal("noise0", Pins("B13"), IOStandard("LVCMOS33")),
Subsignal("noise1", Pins("B14"), IOStandard("LVCMOS33")),
Subsignal("ana_vn", Pins("K9")), # no I/O standard as this is a dedicated pin
Subsignal("ana_vp", Pins("J10")), # no I/O standard as this is a dedicated pin
Subsignal("noise0_n", Pins("A13"), IOStandard("LVCMOS33")), # PATCH
),
("lpclk", 0, Pins("N15"), IOStandard("LVCMOS18")), # wifi_lpclk
# Power control signals
("power", 0,
Subsignal("audio_on", Pins("G13"), IOStandard("LVCMOS33")),
Subsignal("fpga_sys_on", Pins("N13"), IOStandard("LVCMOS18")),
# Subsignal("noisebias_on", Pins("A13"), IOStandard("LVCMOS33")), # PATCH
Subsignal("allow_up5k_n", Pins("U7"), IOStandard("LVCMOS18")),
Subsignal("pwr_s0", Pins("U6"), IOStandard("LVCMOS18")),
# Subsignal("pwr_s1", Pins("L13"), IOStandard("LVCMOS18")), # PATCH
# Noise generator
Subsignal("noise_on", Pins("P14 R13"), IOStandard("LVCMOS18")),
Misc("SLEW=SLOW"),
),
# Audio interface
("i2s", 0,
Subsignal("clk", Pins("D14")),
Subsignal("tx", Pins("D12")), # au_sdi1
Subsignal("rx", Pins("C13")), # au_sdo1
Subsignal("sync", Pins("B15")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"), Misc("DRIVE=4"),
),
# ("i2s", 1, # speaker
# Subsignal("clk", Pins("F14")),
# Subsignal("tx", Pins("A15")), # au_sdi2
# Subsignal("sync", Pins("B17")),
# IOStandard("LVCMOS33"),
# Misc("SLEW=SLOW"), Misc("DRIVE=4"),
# ),
("au_mclk", 0, Pins("D18"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW"), Misc("DRIVE=8")),
# I2C1 bus -- to RTC and audio CODEC
("i2c", 0,
Subsignal("scl", Pins("C14"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("A14"), IOStandard("LVCMOS33")),
Misc("SLEW=SLOW"),
),
# RTC interrupt
("rtc_irq", 0, Pins("N5"), IOStandard("LVCMOS18")),
# COM interface to UP5K
("com", 0,
Subsignal("csn", Pins("T15"), IOStandard("LVCMOS18")),
Subsignal("cipo", Pins("P16"), IOStandard("LVCMOS18")),
Subsignal("copi", Pins("N18"), IOStandard("LVCMOS18")),
Subsignal("sclk", Pins("R16"), IOStandard("LVCMOS18")),
),
("com_irq", 0, Pins("M16"), IOStandard("LVCMOS18")),
# Top-side internal FPC header (B18 and D15 are used by the serial bridge)
("gpio", 0, Pins("A16 B16 D16"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
# Keyboard scan matrix
("kbd", 0,
# "key" 0-8 are rows, 9-18 are columns
# column scan with 1's, so PD to default 0
Subsignal("row", Pins("F15 E17 G17 E14 E15 H15 G15 H14 H16"), Misc("PULLDOWN True")),
Subsignal("col", Pins("H17 E18 F18 G18 E13 H18 F13 H13 J13 K13")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# LCD interface
("lcd", 0,
Subsignal("sclk", Pins("A17")),
Subsignal("scs", Pins("C18")),
Subsignal("si", Pins("D17")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
Misc("DRIVE=4"),
),
# SD card (TF) interface
("sdcard", 0,
Subsignal("data", Pins("J15 J14 K16 K14"), Misc("PULLUP True")),
Subsignal("cmd", Pins("J16"), Misc("PULLUP True")),
Subsignal("clk", Pins("G16")),
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW")
),
# SPI Flash
("spiflash_4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("dq", Pins("K17 K18 L14 M15")),
IOStandard("LVCMOS18")
),
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("copi", Pins("K17")),
Subsignal("cipo", Pins("K18")),
Subsignal("wp", Pins("L14")), # provisional
Subsignal("hold", Pins("M15")), # provisional
IOStandard("LVCMOS18")
),
("spiflash_8x", 0, # clock needs a separate override to meet timing
Subsignal("cs_n", Pins("M13")),
Subsignal("dq", Pins("K17 K18 L14 M15 L17 L18 M14 N14")),
Subsignal("dqs", Pins("R14")),
Subsignal("ecs_n", Pins("L16")),
Subsignal("sclk", Pins("L13")),
IOStandard("LVCMOS18"),
Misc("SLEW=SLOW"),
),
# SRAM
("sram", 0,
Subsignal("adr", Pins(
"V12 M5 P5 N4 V14 M3 R17 U15",
"M4 L6 K3 R18 U16 K1 R5 T2",
"U1 N1 L5 K2 M18 T6"),
IOStandard("LVCMOS18")),
Subsignal("ce_n", Pins("V5"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("oe_n", Pins("U12"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("we_n", Pins("K4"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("zz_n", Pins("V17"), IOStandard("LVCMOS18"), Misc("PULLUP True")),
Subsignal("d", Pins(
"M2 R4 P2 L4 L1 M1 R1 P1",
"U3 V2 V4 U2 N2 T1 K6 J6",
"V16 V15 U17 U18 P17 T18 P18 M17",
"N3 T4 V13 P15 T14 R15 T3 R7"),
IOStandard("LVCMOS18")),
Subsignal("dm_n", Pins("V3 R2 T5 T13"), IOStandard("LVCMOS18")),
),
]
# use this config to wire the debug bridge UART to the Rpi
_io_uart_debug = [
("debug", 0, # wired to the Rpi
Subsignal("tx", Pins("V6")),
Subsignal("rx", Pins("V7")),
IOStandard("LVCMOS18"),
Misc("SLEW=SLOW"),
),
("serial", 0, # wired to the internal flex
Subsignal("tx", Pins("B18")), # debug0 breakout
Subsignal("rx", Pins("D15")), # debug1
IOStandard("LVCMOS33"),
Misc("SLEW=SLOW"),
),
]
# use this config to wire the console UART to the Rpi, and debug bridge to GPIOs
_io_uart_debug_swapped = [
("serial", 0, # wired to the RPi
Subsignal("tx", Pins("V6")),
Subsignal("rx", Pins("V7")),
IOStandard("LVCMOS18"),
),
("debug", 0, # wired to the internal flex
Subsignal("tx", Pins("B18")), # debug0 breakout
Subsignal("rx", Pins("D15")), # debug1
IOStandard("LVCMOS33"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
def __init__(self, io, toolchain="vivado", programmer="vivado", part="50", encrypt=False, make_mod=False, bbram=False):
part = "xc7s" + part + "-csga324-1il"
XilinxPlatform.__init__(self, part, io, toolchain=toolchain)
# NOTE: to do quad-SPI mode, the QE bit has to be set in the SPINOR status register. OpenOCD
# won't do this natively, have to find a work-around (like using iMPACT to set it once)
self.add_platform_command(
"set_property CONFIG_VOLTAGE 1.8 [current_design]")
self.add_platform_command(
"set_property CFGBVS VCCO [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]")
self.toolchain.bitstream_commands = [
"set_property CONFIG_VOLTAGE 1.8 [current_design]",
"set_property CFGBVS GND [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
]
if encrypt:
type = 'eFUSE'
if bbram:
type = 'BBRAM'
self.toolchain.bitstream_commands += [
"set_property BITSTREAM.ENCRYPTION.ENCRYPT YES [current_design]",
"set_property BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT {} [current_design]".format(type),
"set_property BITSTREAM.ENCRYPTION.KEYFILE ../../dummy.nky [current_design]"
]
self.toolchain.additional_commands += \
["write_cfgmem -verbose -force -format bin -interface spix1 -size 64 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.toolchain.additional_commands += [
"report_timing -delay_type min_max -max_paths 10 -slack_less_than 0 -sort_by group -input_pins -routable_nets -name failures -file timing-failures.txt"
]
# this routine retained in case we have to re-explore the bitstream to find the location of the ROM LUTs
if make_mod:
# build a version of the bitstream with a different INIT value for the ROM lut, so the offset frame can
# be discovered by diffing
for bit in range(0, 32):
for lut in range(4):
if lut == 0:
lutname = 'A'
elif lut == 1:
lutname = 'B'
elif lut == 2:
lutname = 'C'
else:
lutname = 'D'
self.toolchain.additional_commands += ["set_property INIT 64'hA6C355555555A6C3 [get_cells KEYROM" + str(bit) + lutname + "]"]
self.toolchain.additional_commands += ["write_bitstream -bin_file -force top-mod.bit"]
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-1.8v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported".format(self.programmer))
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module, AutoCSR):
def __init__(self, platform, sys_clk_freq, spinor_edge_delay_ns=2.5):
self.warm_reset = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_spi = ClockDomain()
self.clock_domains.cd_lpclk = ClockDomain()
self.clock_domains.cd_spinor = ClockDomain()
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk50 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
self.clock_domains.cd_usb_12 = ClockDomain()
# # #
sysclk_ns = 1e9 / sys_clk_freq
# convert delay request in ns to degrees, where 360 degrees is one whole clock period
phase_f = (spinor_edge_delay_ns / sysclk_ns) * 360
# round phase to the nearest multiple of 7.5 (needs to be a multiple of 45 / CLKOUT2_DIVIDE = 45 / 6 = 7.5
# note that CLKOUT2_DIVIDE is automatically calculated by mmcm.create_clkout() below
phase = round(phase_f / 7.5) * 7.5
clk32khz = platform.request("lpclk")
self.specials += Instance("BUFG", i_I=clk32khz, o_O=self.cd_lpclk.clk)
platform.add_platform_command("create_clock -name lpclk -period {:0.3f} [get_nets lpclk]".format(1e9 / 32.768e3))
clk12 = platform.request("clk12")
# Note: below feature cannot be used because Litex appends this *after* platform commands! This causes the generated
# clock derived constraints immediately below to fail, because .xdc file is parsed in-order, and the main clock needs
# to be created before the derived clocks. Instead, we use the line afterwards.
# platform.add_period_constraint(clk12, 1e9 / 12e6)
platform.add_platform_command("create_clock -name clk12 -period {:0.3f} [get_nets clk12]".format(1e9 / 12e6))
# The above constraint must strictly proceed the below create_generated_clock constraints in the .XDC file
# This allows PLLs/MMCMEs to be placed anywhere and reference the input clock
self.clk12_bufg = Signal()
self.specials += Instance("BUFG", i_I=clk12, o_O=self.clk12_bufg)
self.submodules.mmcm = mmcm = S7MMCM(speedgrade=-1)
self.comb += mmcm.reset.eq(self.warm_reset)
mmcm.register_clkin(self.clk12_bufg, 12e6)
# we count on clocks being assigned to the MMCME2_ADV in order. If we make more MMCME2 or shift ordering, these constraints must change.
mmcm.create_clkout(self.cd_usb_48, 48e6) # 48 MHz for USB
platform.add_platform_command("create_generated_clock -name usb_48 [get_pins MMCME2_ADV/CLKOUT0]")
mmcm.create_clkout(self.cd_spi, 20e6)
platform.add_platform_command("create_generated_clock -name spi_clk [get_pins MMCME2_ADV/CLKOUT1]")
mmcm.create_clkout(self.cd_spinor, sys_clk_freq, phase=phase) # delayed version for SPINOR cclk (different from COM SPI above)
platform.add_platform_command("create_generated_clock -name spinor [get_pins MMCME2_ADV/CLKOUT2]")
mmcm.create_clkout(self.cd_clk200, 200e6) # 200MHz required for IDELAYCTL
platform.add_platform_command("create_generated_clock -name clk200 [get_pins MMCME2_ADV/CLKOUT3]")
mmcm.create_clkout(self.cd_clk50, 50e6) # 50MHz for SHA-block
platform.add_platform_command("create_generated_clock -name clk50 [get_pins MMCME2_ADV/CLKOUT4]")
mmcm.create_clkout(self.cd_usb_12, 12e6) # 12 MHz for USB
platform.add_platform_command("create_generated_clock -name usb_12 [get_pins MMCME2_ADV/CLKOUT5]")
mmcm.create_clkout(self.cd_sys, sys_clk_freq, margin=0) # should be precise solution by design
platform.add_platform_command("create_generated_clock -name sys_clk [get_pins MMCME2_ADV/CLKOUT6]")
mmcm.expose_drp()
# Add an IDELAYCTRL primitive for the SpiOpi block
self.submodules += S7IDELAYCTRL(self.cd_clk200, reset_cycles=32) # 155ns @ 200MHz, min 59.28ns
# WarmBoot -----------------------------------------------------------------------------------------
class WarmBoot(Module, AutoCSR):
def __init__(self, parent, reset_vector=0):
self.ctrl = CSRStorage(size=8)
self.addr = CSRStorage(size=32, reset=reset_vector)
self.do_reset = Signal()
# "Reset Key" is 0xac (0b101011xx)
self.comb += self.do_reset.eq((self.ctrl.storage & 0xfc) == 0xac)
# BtEvents -----------------------------------------------------------------------------------------
class BtEvents(Module, AutoCSR, AutoDoc):
def __init__(self, com, rtc):
self.submodules.ev = EventManager()
self.ev.com_int = EventSourcePulse() # rising edge triggered
self.ev.rtc_int = EventSourceProcess() # falling edge triggered
self.ev.finalize()
com_int = Signal()
rtc_int = Signal()
self.specials += MultiReg(com, com_int)
self.specials += MultiReg(rtc, rtc_int)
self.comb += self.ev.com_int.trigger.eq(com_int)
self.comb += self.ev.rtc_int.trigger.eq(rtc_int)
# BtPower ------------------------------------------------------------------------------------------
class BtPower(Module, AutoCSR, AutoDoc):
def __init__(self, pads, revision='evt'):
self.intro = ModuleDoc("""BtPower - power control pins
""")
self.power = CSRStorage(8, fields=[
CSRField("audio", size=1, description="Write `1` to power on the audio subsystem"),
CSRField("self", size=1, description="Writing `1` forces self power-on (overrides the EC's ability to power me down)", reset=1),
CSRField("ec_snoop", size=1, description="Writing `1` allows the insecure EC to snoop a couple keyboard pads for wakeup key sequence recognition"),
CSRField("state", size=2, description="Current SoC power state. 0x=off or not ready, 10=on and safe to shutdown, 11=on and not safe to shut down, resets to 01 to allow extSRAM access immediately during init", reset=1),
CSRField("noisebias", size=1, description="Writing `1` enables the primary bias supply for the noise generator"),
CSRField("noise", size=2, description="Controls which of two noise channels are active; all combos valid. noisebias must be on first."),
CSRField("reset_ec", size=1, description="Writing a `1` forces EC into reset. Requires write of `0` to release reset."),
CSRField("up5k_on", size=1, description="Writing a `1` pulses the UP5K domain to turn on", pulse=True),
CSRField("boostmode", size=1, description="Writing a `1` causes the USB port to source 5V. To be active only when playing the host role."),
CSRField("selfdestruct", size=1, description="Set this bit to clear BBRAM AES key (if used) and cut power in an annoying-to-reset fashion")
])
# future-proofing this: we might want to add e.g. PWM levels and so forth, so give it its own register
self.vibe = CSRStorage(1, description="Vibration motor configuration register", fields=[
CSRField("vibe", size=1, description="Turn on vibration motor"),
])
self.comb += [
pads.audio_on.eq(self.power.fields.audio),
pads.fpga_sys_on.eq(self.power.fields.self),
# This signal automatically enables snoop when SoC is powered down
pads.allow_up5k_n.eq(~self.power.fields.ec_snoop),
# Ensure SRAM isolation during reset (CE & ZZ = 1 by pull-ups)
pads.pwr_s0.eq(self.power.fields.state[0] & ~ResetSignal()),
]
if revision != 'modnoise':
self.comb += pads.noise_on.eq(self.power.fields.noise),
if revision == 'dvt' or revision == 'pvt':
self.reset_ec = TSTriple(1)
if revision == 'dvt':
self.specials += self.reset_ec.get_tristate(pads.reset_ec_n)
self.comb += self.reset_ec.i.eq(0) # reset is an active low signal
else:
self.specials += self.reset_ec.get_tristate(pads.reset_ec)
self.comb += self.reset_ec.i.eq(1) # reset is an active high signal
self.comb += [
pads.pwr_s1.eq(self.power.fields.state[1]),
pads.noisebias_on.eq(self.power.fields.noisebias),
pads.vibe_on.eq(self.vibe.fields.vibe),
self.reset_ec.oe.eq(self.power.fields.reset_ec), # drive reset low only when reset_ec is asserted, otherwise, Hi-Z
]
self.submodules.ev = EventManager()
self.ev.usb_attach = EventSourcePulse(description="USB attach event")
self.ev.finalize()
usb_attach = Signal()
usb_attach_r = Signal()
self.specials += MultiReg(pads.cc_id, usb_attach)
self.sync += [
usb_attach_r.eq(usb_attach),
self.ev.usb_attach.trigger.eq(~usb_attach & usb_attach_r), # falling edge trigger
]
up5k_on_pulse = 0.20 # pulse up5k for 200ms to turn it on and have it keep itself on
up5k_on_count = Signal(26, reset=int(up5k_on_pulse * 100e6))
self.sync += [
If(up5k_on_count > 0,
pads.up5k_on.eq(1),
).Else(
pads.up5k_on.eq(0)
),
If(self.power.fields.up5k_on,
up5k_on_count.eq(int(up5k_on_pulse * 100e6))
).Elif( up5k_on_count > 0,
up5k_on_count.eq(up5k_on_count - 1),
).Else(
up5k_on_count.eq(0)
)
]
if revision == 'pvt':
self.comb += pads.boostmode.eq(self.power.fields.boostmode)
self.comb += pads.selfdestruct.eq(self.power.fields.selfdestruct)
# ModNoise ------------------------------------------------------------------------------------------
class ModNoise(Module, AutoCSR, AutoDoc):
def __init__(self, pads):
self.intro = ModuleDoc("""Modular Noise generator
Modular noise generator driver. Generates non-overlapping clocks, and aggregates
incoming noise.
Op-amp bandwidth is 1MHz, slew rate of 2V/us. Cap settling time is probably around
3-4us per phase. Target 4.95us/phase, with a dead time of 50ns between phases. This
should yield around 100kbps raw noise generation rate, which roughly matches the
maximum rate at which 256-bit DH key exchanges can be done using the Curve25519 engine.
""")
self.phase0 = Signal()
self.phase1 = Signal()
self.noiseon = Signal()
self.noisein = Signal()
self.comb += [
pads.phase0.eq(self.phase0),
pads.phase1.eq(self.phase1),
pads.noise_on.eq(self.noiseon),
self.noisein.eq(pads.noise_in),
]
noisesync = Signal()
self.specials += MultiReg(self.noisein, noisesync)
self.ctl = CSRStorage(fields=[
CSRField("ena", size=1, description="Power on and enable TRNG.", reset=0),
CSRField("period", size=20, description="Duration of one phase in sysclk periods", reset=495),
CSRField("deadtime", size=10, description="Duration of deadtime between nonoverlaps in sysclk periods", reset=5),
])
self.comb += self.noiseon.eq(self.ctl.fields.ena)
self.rand = CSRStatus(fields=[
CSRField("rand", size=32, description="Random data shifted into a register for easier collection", reset=0xDEADBEEF),
])
self.status = CSRStatus(fields=[
CSRField("fresh", size=1, description="WHen set, the rand register contains a fresh set of bits to read; cleared by reading the `rand` register")
])